Intel BX80571E7500 Programming Manual - Page 59
Table 2-26. S_MSR_PMON_SUMMARY Register Fields, Table 2-27. S_CSR_PMON_GLOBAL_CTL Register Fields,
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field ig ov_r ov_s ig ov_mb ig ov_c_l ig ov_c_r Table 2-26. S_MSR_PMON_SUMMARY Register Fields Bits HW Reset Val Description 63:20 19 18 17 16 15:3 2 1 0 Read zero; writes ignored. 0 Overflow in R Box In S-Box0, indicates overflow from Left R-Box In S-Box1, indicates overflow from Right R-Box 0 Overflow in S Box Read zero; writes ignored. 0 Overflow in M- or B-Box Read zero; writes ignored. 0 Overflow in 'left' C-Boxes In SBOX0, indicates overflow in C-Box 0 or 1. In SBOX1, indicates overflow in C-Box 4 or 5. Read zero; writes ignored. 0 Overflow in 'right' C-Boxes In SBOX0, indicates overflow in C-Box 2 or 3. In SBOX1, indicates overflow in C-Box 6 or 7. 2.5.3.2 S-Box Box Level PMON state The following registers represent the state governing all box-level PMUs in the S-Box. The _GLOBAL_CTL register contains the bits used to enable monitoring. It is necessary to set the .ctr_en bit to 1 before the corresponding data register can collect events. If an overflow is detected from one of the S-Box PMON registers, the corresponding bit in the _GLOBAL_STATUS.ov field will be set. To reset the overflow bits set in the _GLOBAL_STATUS.ov field, a user must set the corresponding bits in the _GLOBAL_OVF_CTL.clr_ov field before beginning a new sample interval. Table 2-27. S_CSR_PMON_GLOBAL_CTL Register Fields Field ctr_en Bits HW Reset Val Description 3:0 0 Must be set to enable each SBOX counter (bit 0 to enable ctr0, etc) NOTE: U-Box enable and per counter enable must also be set to fully enable the counter. Table 2-28. S_MSR_PMON_GLOBAL_STATUS Register Fields Field ov Bits HW Reset Val Description 3:0 0 If an overflow is detected from the corresponding SBOX PMON register, it's overflow bit will be set. 2-47