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Intel BX80571E7500 Programming Manual - Page 102

Eot_occupancy, Flits_recv_err, Flits_recv_spec, Flits_sent, Global_arb_bid

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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING EOT_OCCUPANCY • Title: EOT Occupancy • Category: RIX • [Bit(s)] Value: [21]0x0, Max. Inc/Cyc: 1, • Definition: Used with MC field. Report a rolling count whenever a 7b counter (count == 128) over- flows for the selected MC's allocation into EOT. • NOTE: This basically counts VNA. Extension --HOM_VN0 HOM_VN1 NDR DRS_VN0 SNP NCB NCS DRS_VN1 --- Table 2-57. Unit Masks for EOT_ROLL_DEPTH_ACC IPERF Bit Values [20:17] Description b0000 (*nothing will be counted*) b0001 Home (VN0) Messages b0010 Home (VN1) Messages b0011 Non-Data Response Messages b0100 Data Response (VN0) Messages b0101 Snoop Messages b0110 Non-Coherent Bypass Messages b0111 Non-Coherent Standard Messages b1000 Data Response (VN1) Messages b1001-b1111 (*nothing will be counted*) FLITS_RECV_ERR • Title: Error Flits Received • Category: RIX • [Bit(s)] Value: [24]0x1, Max. Inc/Cyc: 1, • Definition: Counts all flits received which caused CRC Error. FLITS_RECV_SPEC • Title: Special Flits Received • Category: RIX • [Bit(s)] Value: [25]0x1, Max. Inc/Cyc: 1, • Definition: Counts all special flits received. FLITS_SENT • Title: Flits Sent • Category: RIX • [Bit(s)] Value: [31]0x1, Max. Inc/Cyc: 1, • Definition: Counts all flits. Output queue receives active beat. GLOBAL_ARB_BID • Title: Global ARB Bids • Category: QLX • [Bit(s)] Value: [3:0]0x2, Max. Inc/Cyc: 1, • Definition: Count global arbitration bids from the port. 2-90

Section	Page
CHAPTER 1 INTRODUCTION	9
1.1 INTRODUCTION	9
1.2 Uncore PMU Overview	9
1.3 Uncore PMU Summary Tables	10
1.4 References	11
CHAPTER 2 UNCORE PERFORMANCE MONITORING	13
2.1 Global Performance Monitoring Control	13
2.1.1 Counter Overflow	13
2.1.1.1 Freezing on Counter Overflow	13
2.1.1.2 PMI on Counter Overflow	13
2.1.2 Setting up a Monitoring Session	13
2.1.3 Reading the Sample Interval	14
2.1.4 Enabling a New Sample Interval from Frozen Counters	14
2.1.5 Global Performance Monitors	15
2.1.5.1 Global PMON Global Control/Status Registers	15
2.2 U-Box Performance Monitoring	17
2.2.1 U-Box PMON Summary	17
2.2.1.1 U-Box Box Level PMON State	17
2.2.1.2 U-Box PMON state - Counter/Control Pairs	17
2.2.2 U-Box Performance Monitoring Events	18
2.2.3 U-Box Events Ordered By Code	18
2.2.4 U-Box Performance Monitor Event List	19
2.3 C-Box Performance Monitoring	21
2.3.1 Overview of the C-Box	21
2.3.2 C-Box Performance Monitoring Overview	21
2.3.2.1 C-Box PMU - Overflow, Freeze and Unfreeze	21
2.3.3 C-BOX Performance Monitors	22
2.3.3.1 C-Box Box Level PMON state	25
2.3.3.2 C-Box PMON state - Counter/Control Pairs	26
2.3.4 C-BOX Performance Monitoring Events	28
2.3.4.1 An Overview:	28
2.3.4.2 Acronyms frequently used in C-Box Events:	28
2.3.4.3 The Queues:	29
2.3.4.4 Detecting Performance Problems in the C-Box Pipeline:	29
2.3.5 C-Box Events Ordered By Code	29
2.3.6 C-Box Performance Monitor Event List	30
2.4 B-Box Performance Monitoring	41
2.4.1 Overview of the B-Box	41
2.4.2 B-Box Performance Monitoring Overview	41
2.4.2.1 B-Box PMU - On Overflow and the Consequences (PMI/Freeze)	41
2.4.3 B-BOX Performance Monitors	42
2.4.3.1 B-Box Box Level PMON state	42
2.4.3.2 B-Box PMON state - Counter/Control Pairs + Filters	43
2.4.4 B-Box Performance Monitoring Events	45
2.4.4.1 On the ARBQ:	45
2.4.4.2 On the Major B-Box Structures:	46
2.4.4.3 On InvItoE Transactions:	46
2.4.5 B-Box Events Ordered By Code	46
2.4.6 B-Box Performance Monitor Event List	48
2.5 S-Box Performance Monitoring	57
2.5.1 Overview of the S-Box	57
2.5.2 S-Box Performance Monitoring Overview	57
2.5.2.1 S-Box PMU - Overflow, Freeze and Unfreeze	57
2.5.3 S-BOX Performance Monitors	57
2.5.3.1 S-Box PMON for Global State	58
2.5.3.2 S-Box Box Level PMON state	59
2.5.3.3 S-Box PMON state - Counter/Control Pairs + Filters	60
2.5.3.4 S-Box Registers for Mask/Match Facility	61
2.5.4 S-BOX Performance Monitoring Events	63
2.5.4.1 An Overview	63
2.5.4.2 On Queue Occupancy Usage	63
2.5.4.3 On Packet Transmission Events	64
2.5.5 S-Box Events Ordered By Code	65
2.5.6 S-Box Performance Monitor Event List	67
2.6 R-Box Performance Monitoring	84
2.6.1 Overview of the R-Box	84
2.6.1.1 R-Box Input Port	84
2.6.1.2 R-Box Arbitration Control	84
2.6.1.3 R-Box Output Port	85
2.6.1.4 R-Box Link Layer Resources	85
2.6.2 R-Box Performance Monitoring Overview	85
2.6.2.1 Choosing An Event To Monitor - Example	85
2.6.2.2 R-Box PMU - Overflow, Freeze and Unfreeze	86
2.6.3 R-BOX Performance Monitors	86
2.6.3.1 R-Box Performance Monitors To Port Mapping	89
2.6.3.2 R-Box Box Level PMON state	90
2.6.3.3 R-Box PMON state - Counter/Control Pairs + Filters	90
2.6.3.4 R-Box IPERF Performance Monitoring Control Registers	94
2.6.3.5 R-Box QLX Performance Monitoring Control Registers	95
2.6.3.6 R-Box Registers for Mask/Match Facility	96
2.6.4 R-BOX Performance Monitoring Events	99
2.6.4.1 An Overview:	99
2.6.5 R-Box Events Ordered By Code	99
2.6.6 R-Box Performance Monitor Event List	100
2.7 M-Box Performance Monitoring	107
2.7.1 Overview of the M-Box	107
2.7.2 Functional Overview	107
2.7.2.1 Intel ® 7500 Scalable Memory Buffer	108
2.7.3 M-Box Performance Monitoring Overview	108
2.7.3.1 Choosing An Event To Monitor - Example using subcontrol registers	108
2.7.3.2 M-Box PMU - Overflow, Freeze and Unfreeze	109
2.7.4 M-BOX Performance Monitors	110
2.7.4.1 M-Box Box Level PMON state	111
2.7.4.2 M-Box PMON state - Counter/Control Pairs	112
2.7.4.3 M-Box PMU Filter Registers	114
2.7.4.4 M-Box PMU Subcontrol Registers - Subunit descriptions	114
2.7.5 M-Box Performance Monitoring Events	121
2.7.5.1 An Overview:	121
2.7.6 M-Box Events Ordered By Code	122
2.7.7 M-Box Performance Monitor Event List	123
2.8 W-Box Performance Monitoring	136
2.8.1 Overview of the W-Box	136
2.8.2 W-Box Performance Monitoring Overview	136
2.8.2.1 W-Box PMU - Overflow, Freeze and Unfreeze	136
2.8.3 W-BOX Performance Monitors	137
2.8.3.1 W-Box Box Level PMON state	137
2.8.3.2 W-Box PMON state - Counter/Control Pairs	138
2.8.4 W-BOX Performance Monitoring Events	140
2.8.4.1 An Overview:	140
2.8.5 W-Box Events Ordered By Code	140
2.8.6 W-Box Performance Monitor Event List	140

Match case Limit results 1 per page

NTEL

® X

EON

® P

ROCESSOR

7500 S

ERIES

NCORE

ROGRAMMING

UIDE

UNCORE PERFORMANCE MONITORING

2-90

EOT_OCCUPANCY

• Title:

EOT Occupancy

• Category:

RIX

• [Bit(s)] Value:

[21]0x0,

Max. Inc/Cyc:

• Definition:

Used with MC field. Report a rolling count whenever a 7b counter (count == 128) over-

flows for the selected MC’s allocation into EOT.

• NOTE:

This basically counts VNA.

FLITS_RECV_ERR

• Title:

Error Flits Received

• Category:

RIX

• [Bit(s)] Value:

[24]0x1,

Max. Inc/Cyc:

• Definition:

Counts all flits received which caused CRC Error.

FLITS_RECV_SPEC

• Title:

Special Flits Received

• Category:

RIX

• [Bit(s)] Value:

[25]0x1,

Max. Inc/Cyc:

• Definition:

Counts all special flits received.

FLITS_SENT

• Title:

Flits Sent

• Category:

RIX

• [Bit(s)] Value:

[31]0x1,

Max. Inc/Cyc:

• Definition:

Counts all flits. Output queue receives active beat.

GLOBAL_ARB_BID

• Title:

Global ARB Bids

• Category:

QLX

• [Bit(s)] Value:

[3:0]0x2,

Max. Inc/Cyc:

• Definition:

Count global arbitration bids from the port.

Table 2-57. Unit Masks for EOT_ROLL_DEPTH_ACC

Extension

IPERF Bit

Values

[20:17]

Description

---

b0000

(*nothing will be counted*)

HOM_VN0

b0001

Home (VN0) Messages

HOM_VN1

b0010

Home (VN1) Messages

NDR

b0011

Non-Data Response Messages

DRS_VN0

b0100

Data Response (VN0) Messages

SNP

b0101

Snoop Messages

NCB

b0110

Non-Coherent Bypass Messages

NCS

b0111

Non-Coherent Standard Messages

DRS_VN1

b1000

Data Response (VN1) Messages

---

b1001-b1111

(*nothing will be counted*)