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FVC_EV1

UPC - 735858206969

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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING FVC_EVx.bcmd_match event may be monitored at any given time. The same holds true for FVC_EVx.resp_match Extension SMI_CRC_ERR MEM_ECC_ERR POISON_TXN ALERT_FRAMES FAST_RESET BBOX_CMDS.READS BBOX_CMDS.WRITES BBOX_RSP.ACK BBOX_RSP.RETRY BBOX_RSP.COR BBOX_RSP.UNCOR BBOX_RSP.SPEC_ACK BBOX_RSP.SPR_ACK --BBOX_RSP.SPR_UNCOR SMI_NB_TRIG Table 2-89. Unit Masks for FVC_EV0 FVC FVC FVC [13:11] [10:8] [7:5] Description 0x0 Count link level Intel SMI CRC errors 0x1 Count memory ECC errors (that is not a link-level CRC error) 0x2 Count poison (directory of a write to memory was encoded as poisoned) transactions 0x3 Counts alert frames 0x4 Fast reset request from M-Boxes 0x5 0x0 Reads commands to M box from B box (e.g. reads from memory) 0x5 0x1 Write commands from B box to M box (e.g. writes to memory) 0x6 0x0 Counts positive acknowledgements. No error was detected. 0x6 0x1 Count Retry Responses. Possibly a correctable error. Retries are generated until it is decided that the error was either correctable or uncorrectable. 0x6 0x2 0x6 0x3 0x6 0x4 0x6 0x5 0x6 0x6 0x6 0x7 0x7 Counts corrected (for example, after error trials or just by a retry) Count Uncorrectable Responses. Speculative positive acknowledgement for optimized read flow. No error was detected for the transaction. Count positive acknowledgements for command to misbehaving DIMM during sparing. No error was detected for the transaction. (*nothing will be counted*) Counts Uncorrectable responses to B-Box as a result of commands issued to misbehaving DIMM during sparing Select Intel SMI Northbound debug event bits from Intel SMI status frames as returned from the Intel 7500 Scalable Memory Buffers. Used for Debug purposes FVC_EV1 • Title: FVC Event 1 • Category: FVC Events • Event Code: 0x0e, Max. Inc/Cyc: 1, • Definition: Measure an FVC related event. • NOTE: It is possible to program the FVC register such that up to 4 events from the FVC can be independently monitored. However, the bcmd_match and resp_match subevents depend on the setting of additional bits in the FVC register (11:9 and 8:5 respectively). Therefore, only ONE FVC_EVx.bcmd_match event may be monitored at any given time. The same holds true for FVC_EVx.resp_match Extension SMI_CRC_ERR MEM_ECC_ERR Table 2-90. Unit Masks for FVC_EV1 (Sheet 1 of 2) FVC FVC FVC [16:14] [10:8] [7:5] Description 0x0 Count link level Intel SMI CRC errors 0x1 Count memory ECC errors (that is not a link-level CRC error) 2-115

Section	Page
CHAPTER 1 INTRODUCTION	9
1.1 INTRODUCTION	9
1.2 Uncore PMU Overview	9
1.3 Uncore PMU Summary Tables	10
1.4 References	11
CHAPTER 2 UNCORE PERFORMANCE MONITORING	13
2.1 Global Performance Monitoring Control	13
2.1.1 Counter Overflow	13
2.1.1.1 Freezing on Counter Overflow	13
2.1.1.2 PMI on Counter Overflow	13
2.1.2 Setting up a Monitoring Session	13
2.1.3 Reading the Sample Interval	14
2.1.4 Enabling a New Sample Interval from Frozen Counters	14
2.1.5 Global Performance Monitors	15
2.1.5.1 Global PMON Global Control/Status Registers	15
2.2 U-Box Performance Monitoring	17
2.2.1 U-Box PMON Summary	17
2.2.1.1 U-Box Box Level PMON State	17
2.2.1.2 U-Box PMON state - Counter/Control Pairs	17
2.2.2 U-Box Performance Monitoring Events	18
2.2.3 U-Box Events Ordered By Code	18
2.2.4 U-Box Performance Monitor Event List	19
2.3 C-Box Performance Monitoring	21
2.3.1 Overview of the C-Box	21
2.3.2 C-Box Performance Monitoring Overview	21
2.3.2.1 C-Box PMU - Overflow, Freeze and Unfreeze	21
2.3.3 C-BOX Performance Monitors	22
2.3.3.1 C-Box Box Level PMON state	25
2.3.3.2 C-Box PMON state - Counter/Control Pairs	26
2.3.4 C-BOX Performance Monitoring Events	28
2.3.4.1 An Overview:	28
2.3.4.2 Acronyms frequently used in C-Box Events:	28
2.3.4.3 The Queues:	29
2.3.4.4 Detecting Performance Problems in the C-Box Pipeline:	29
2.3.5 C-Box Events Ordered By Code	29
2.3.6 C-Box Performance Monitor Event List	30
2.4 B-Box Performance Monitoring	41
2.4.1 Overview of the B-Box	41
2.4.2 B-Box Performance Monitoring Overview	41
2.4.2.1 B-Box PMU - On Overflow and the Consequences (PMI/Freeze)	41
2.4.3 B-BOX Performance Monitors	42
2.4.3.1 B-Box Box Level PMON state	42
2.4.3.2 B-Box PMON state - Counter/Control Pairs + Filters	43
2.4.4 B-Box Performance Monitoring Events	45
2.4.4.1 On the ARBQ:	45
2.4.4.2 On the Major B-Box Structures:	46
2.4.4.3 On InvItoE Transactions:	46
2.4.5 B-Box Events Ordered By Code	46
2.4.6 B-Box Performance Monitor Event List	48
2.5 S-Box Performance Monitoring	57
2.5.1 Overview of the S-Box	57
2.5.2 S-Box Performance Monitoring Overview	57
2.5.2.1 S-Box PMU - Overflow, Freeze and Unfreeze	57
2.5.3 S-BOX Performance Monitors	57
2.5.3.1 S-Box PMON for Global State	58
2.5.3.2 S-Box Box Level PMON state	59
2.5.3.3 S-Box PMON state - Counter/Control Pairs + Filters	60
2.5.3.4 S-Box Registers for Mask/Match Facility	61
2.5.4 S-BOX Performance Monitoring Events	63
2.5.4.1 An Overview	63
2.5.4.2 On Queue Occupancy Usage	63
2.5.4.3 On Packet Transmission Events	64
2.5.5 S-Box Events Ordered By Code	65
2.5.6 S-Box Performance Monitor Event List	67
2.6 R-Box Performance Monitoring	84
2.6.1 Overview of the R-Box	84
2.6.1.1 R-Box Input Port	84
2.6.1.2 R-Box Arbitration Control	84
2.6.1.3 R-Box Output Port	85
2.6.1.4 R-Box Link Layer Resources	85
2.6.2 R-Box Performance Monitoring Overview	85
2.6.2.1 Choosing An Event To Monitor - Example	85
2.6.2.2 R-Box PMU - Overflow, Freeze and Unfreeze	86
2.6.3 R-BOX Performance Monitors	86
2.6.3.1 R-Box Performance Monitors To Port Mapping	89
2.6.3.2 R-Box Box Level PMON state	90
2.6.3.3 R-Box PMON state - Counter/Control Pairs + Filters	90
2.6.3.4 R-Box IPERF Performance Monitoring Control Registers	94
2.6.3.5 R-Box QLX Performance Monitoring Control Registers	95
2.6.3.6 R-Box Registers for Mask/Match Facility	96
2.6.4 R-BOX Performance Monitoring Events	99
2.6.4.1 An Overview:	99
2.6.5 R-Box Events Ordered By Code	99
2.6.6 R-Box Performance Monitor Event List	100
2.7 M-Box Performance Monitoring	107
2.7.1 Overview of the M-Box	107
2.7.2 Functional Overview	107
2.7.2.1 Intel ® 7500 Scalable Memory Buffer	108
2.7.3 M-Box Performance Monitoring Overview	108
2.7.3.1 Choosing An Event To Monitor - Example using subcontrol registers	108
2.7.3.2 M-Box PMU - Overflow, Freeze and Unfreeze	109
2.7.4 M-BOX Performance Monitors	110
2.7.4.1 M-Box Box Level PMON state	111
2.7.4.2 M-Box PMON state - Counter/Control Pairs	112
2.7.4.3 M-Box PMU Filter Registers	114
2.7.4.4 M-Box PMU Subcontrol Registers - Subunit descriptions	114
2.7.5 M-Box Performance Monitoring Events	121
2.7.5.1 An Overview:	121
2.7.6 M-Box Events Ordered By Code	122
2.7.7 M-Box Performance Monitor Event List	123
2.8 W-Box Performance Monitoring	136
2.8.1 Overview of the W-Box	136
2.8.2 W-Box Performance Monitoring Overview	136
2.8.2.1 W-Box PMU - Overflow, Freeze and Unfreeze	136
2.8.3 W-BOX Performance Monitors	137
2.8.3.1 W-Box Box Level PMON state	137
2.8.3.2 W-Box PMON state - Counter/Control Pairs	138
2.8.4 W-BOX Performance Monitoring Events	140
2.8.4.1 An Overview:	140
2.8.5 W-Box Events Ordered By Code	140
2.8.6 W-Box Performance Monitor Event List	140

Match case Limit results 1 per page

NTEL

® X

EON

® P

ROCESSOR

7500 S

ERIES

NCORE

ROGRAMMING

UIDE

UNCORE PERFORMANCE MONITORING

2-115

FVC_EVx.bcmd_match event may be monitored at any given time. The same holds true for

FVC_EVx.resp_match

FVC_EV1

• Title:

FVC Event 1

• Category:

FVC Events

• Event Code:

0x0e,

Max. Inc/Cyc:

• Definition:

Measure an FVC related event.

• NOTE:

It is possible to program the FVC register such that up to 4 events from the FVC can be inde-

pendently monitored. However, the bcmd_match and resp_match subevents depend on the setting of

additional

bits in the FVC register (11:9 and 8:5 respectively). Therefore, only

ONE

FVC_EVx.bcmd_match event may be monitored at any given time. The same holds true for

FVC_EVx.resp_match

Table 2-89. Unit Masks for FVC_EV0

Extension

FVC

[13:11]

FVC

[10:8]

FVC

[7:5]

Description

SMI_CRC_ERR

0x0

Count link level Intel SMI CRC errors

MEM_ECC_ERR

0x1

Count memory ECC errors (that is not a link-level

CRC error)

POISON_TXN

0x2

Count poison (directory of a write to memory was

encoded as poisoned) transactions

ALERT_FRAMES

0x3

Counts alert frames

FAST_RESET

0x4

Fast reset request from M-Boxes

BBOX_CMDS.READS

0x5

0x0

Reads commands to M box from B box (e.g. reads

from memory)

BBOX_CMDS.WRITES

0x5

0x1

Write commands from B box to M box (e.g. writes to

memory)

BBOX_RSP.ACK

0x6

0x0

Counts positive acknowledgements. No error was

detected.

BBOX_RSP.RETRY

0x6

0x1

Count Retry Responses. Possibly a correctable error.

Retries are generated until it is decided that the error

was either correctable or uncorrectable.

BBOX_RSP.COR

0x6

0x2

Counts corrected (for example, after error trials or

just by a retry)

BBOX_RSP.UNCOR

0x6

0x3

Count Uncorrectable Responses.

BBOX_RSP.SPEC_ACK

0x6

0x4

Speculative positive acknowledgement for optimized

read flow. No error was detected for the transaction.

BBOX_RSP.SPR_ACK

0x6

0x5

Count positive acknowledgements for command to

misbehaving DIMM during sparing. No error was

detected for the transaction.

---

0x6

(*nothing will be counted*)

BBOX_RSP.SPR_UNCOR

0x6

0x7

Counts Uncorrectable responses to B-Box as a result

of commands issued to misbehaving DIMM during

sparing

SMI_NB_TRIG

0x7

Select Intel SMI Northbound debug event bits from

Intel SMI status frames as returned from the Intel

7500 Scalable Memory Buffers. Used for Debug

purposes

Table 2-90. Unit Masks for FVC_EV1 (Sheet 1 of 2)