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Intel BX80571E7500 Programming Manual - Page 113

Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register - Field Definitions, Table 2-68. M_MSR_PMU_CNT_{5-0}

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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register - Field Definitions Field ig rsv ig rsv set_flag_sel rsv inc_sel rsv flag_mode wrap_mode storage_mode count_mode pmi_en en Bits HW Reset Val Description 63 62:61 60:25 24:22 21:19 18:14 13:9 8 7 6 5:4 3:2 1 0 0 Read zero; writes ignored. (?) 0 Reserved; Must write to 0 else behavior is undefined. 0 Read zero; writes ignored. (?) 0 Reserved; Must write to 0 else behavior is undefined. 0 Selects the 'set' condition for enable flag. Secondary event select. See Table 2-84, "Performance Monitor Events for M-Box Events" for events elected by this field. NOTE: Bit 7 (flag_mode) must be set to 1 to enable this field. 0 Reserved; Must write to 0 else behavior is undefined. 0 Selects increment signal for this counter. Primary event select. See Table 2-84, "Performance Monitor Events for M-Box Events" for events elected by this field. 0 Reserved; Must write to 0 else behavior is undefined. 0 Enable conditional counting using set_flag_sel 0 Counter wrap mode. If set to 0, this counter will stop counting on detection of over/underflow. If set to 1, this counter will wrap and continue counting on detection of over/underflow. 0 Storage mode. If set to 0, no count enable flag is required. If set to 1, count enable flag must have a value of 1 for counting to occur. 0 00 - count will increase (up) 01 - count will decrease (dn) 10 - count can increase and decrease 0 Enable PMON interrupt on counter over/underflow. 0 Enable counting The M-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by preloading a monitor with a count value of (248 - 1) - N and setting the control register to send a PMI to the U-Box. Upon receipt of the PMI, the U-Box will disable counting ( Section 2.1.1.1, "Freezing on Counter Overflow"). During the interval of time between overflow and global disable, the counter value will wrap and continue to collect events. In this way, software can capture the precise number of events that occurred between the time uncore counting was enabled and when it was disabled (or 'frozen') with minimal skew. If accessible, software can continuously read the data registers without disabling event collection. Table 2-68. M_MSR_PMU_CNT_{5-0} Register - Field Definitions Field event_count Bits HW Reset Val Description 47:0 0 48-bit performance event counter The M-Box also includes a 16b timestamp unit that is incremented each M-Box clock tick. It is a freerunning counter unattached to the rest of the M-Box PMU, meaning it does not generate an event fed to the other counters. 2-101

Section	Page
CHAPTER 1 INTRODUCTION	9
1.1 INTRODUCTION	9
1.2 Uncore PMU Overview	9
1.3 Uncore PMU Summary Tables	10
1.4 References	11
CHAPTER 2 UNCORE PERFORMANCE MONITORING	13
2.1 Global Performance Monitoring Control	13
2.1.1 Counter Overflow	13
2.1.1.1 Freezing on Counter Overflow	13
2.1.1.2 PMI on Counter Overflow	13
2.1.2 Setting up a Monitoring Session	13
2.1.3 Reading the Sample Interval	14
2.1.4 Enabling a New Sample Interval from Frozen Counters	14
2.1.5 Global Performance Monitors	15
2.1.5.1 Global PMON Global Control/Status Registers	15
2.2 U-Box Performance Monitoring	17
2.2.1 U-Box PMON Summary	17
2.2.1.1 U-Box Box Level PMON State	17
2.2.1.2 U-Box PMON state - Counter/Control Pairs	17
2.2.2 U-Box Performance Monitoring Events	18
2.2.3 U-Box Events Ordered By Code	18
2.2.4 U-Box Performance Monitor Event List	19
2.3 C-Box Performance Monitoring	21
2.3.1 Overview of the C-Box	21
2.3.2 C-Box Performance Monitoring Overview	21
2.3.2.1 C-Box PMU - Overflow, Freeze and Unfreeze	21
2.3.3 C-BOX Performance Monitors	22
2.3.3.1 C-Box Box Level PMON state	25
2.3.3.2 C-Box PMON state - Counter/Control Pairs	26
2.3.4 C-BOX Performance Monitoring Events	28
2.3.4.1 An Overview:	28
2.3.4.2 Acronyms frequently used in C-Box Events:	28
2.3.4.3 The Queues:	29
2.3.4.4 Detecting Performance Problems in the C-Box Pipeline:	29
2.3.5 C-Box Events Ordered By Code	29
2.3.6 C-Box Performance Monitor Event List	30
2.4 B-Box Performance Monitoring	41
2.4.1 Overview of the B-Box	41
2.4.2 B-Box Performance Monitoring Overview	41
2.4.2.1 B-Box PMU - On Overflow and the Consequences (PMI/Freeze)	41
2.4.3 B-BOX Performance Monitors	42
2.4.3.1 B-Box Box Level PMON state	42
2.4.3.2 B-Box PMON state - Counter/Control Pairs + Filters	43
2.4.4 B-Box Performance Monitoring Events	45
2.4.4.1 On the ARBQ:	45
2.4.4.2 On the Major B-Box Structures:	46
2.4.4.3 On InvItoE Transactions:	46
2.4.5 B-Box Events Ordered By Code	46
2.4.6 B-Box Performance Monitor Event List	48
2.5 S-Box Performance Monitoring	57
2.5.1 Overview of the S-Box	57
2.5.2 S-Box Performance Monitoring Overview	57
2.5.2.1 S-Box PMU - Overflow, Freeze and Unfreeze	57
2.5.3 S-BOX Performance Monitors	57
2.5.3.1 S-Box PMON for Global State	58
2.5.3.2 S-Box Box Level PMON state	59
2.5.3.3 S-Box PMON state - Counter/Control Pairs + Filters	60
2.5.3.4 S-Box Registers for Mask/Match Facility	61
2.5.4 S-BOX Performance Monitoring Events	63
2.5.4.1 An Overview	63
2.5.4.2 On Queue Occupancy Usage	63
2.5.4.3 On Packet Transmission Events	64
2.5.5 S-Box Events Ordered By Code	65
2.5.6 S-Box Performance Monitor Event List	67
2.6 R-Box Performance Monitoring	84
2.6.1 Overview of the R-Box	84
2.6.1.1 R-Box Input Port	84
2.6.1.2 R-Box Arbitration Control	84
2.6.1.3 R-Box Output Port	85
2.6.1.4 R-Box Link Layer Resources	85
2.6.2 R-Box Performance Monitoring Overview	85
2.6.2.1 Choosing An Event To Monitor - Example	85
2.6.2.2 R-Box PMU - Overflow, Freeze and Unfreeze	86
2.6.3 R-BOX Performance Monitors	86
2.6.3.1 R-Box Performance Monitors To Port Mapping	89
2.6.3.2 R-Box Box Level PMON state	90
2.6.3.3 R-Box PMON state - Counter/Control Pairs + Filters	90
2.6.3.4 R-Box IPERF Performance Monitoring Control Registers	94
2.6.3.5 R-Box QLX Performance Monitoring Control Registers	95
2.6.3.6 R-Box Registers for Mask/Match Facility	96
2.6.4 R-BOX Performance Monitoring Events	99
2.6.4.1 An Overview:	99
2.6.5 R-Box Events Ordered By Code	99
2.6.6 R-Box Performance Monitor Event List	100
2.7 M-Box Performance Monitoring	107
2.7.1 Overview of the M-Box	107
2.7.2 Functional Overview	107
2.7.2.1 Intel ® 7500 Scalable Memory Buffer	108
2.7.3 M-Box Performance Monitoring Overview	108
2.7.3.1 Choosing An Event To Monitor - Example using subcontrol registers	108
2.7.3.2 M-Box PMU - Overflow, Freeze and Unfreeze	109
2.7.4 M-BOX Performance Monitors	110
2.7.4.1 M-Box Box Level PMON state	111
2.7.4.2 M-Box PMON state - Counter/Control Pairs	112
2.7.4.3 M-Box PMU Filter Registers	114
2.7.4.4 M-Box PMU Subcontrol Registers - Subunit descriptions	114
2.7.5 M-Box Performance Monitoring Events	121
2.7.5.1 An Overview:	121
2.7.6 M-Box Events Ordered By Code	122
2.7.7 M-Box Performance Monitor Event List	123
2.8 W-Box Performance Monitoring	136
2.8.1 Overview of the W-Box	136
2.8.2 W-Box Performance Monitoring Overview	136
2.8.2.1 W-Box PMU - Overflow, Freeze and Unfreeze	136
2.8.3 W-BOX Performance Monitors	137
2.8.3.1 W-Box Box Level PMON state	137
2.8.3.2 W-Box PMON state - Counter/Control Pairs	138
2.8.4 W-BOX Performance Monitoring Events	140
2.8.4.1 An Overview:	140
2.8.5 W-Box Events Ordered By Code	140
2.8.6 W-Box Performance Monitor Event List	140

Match case Limit results 1 per page

NTEL

® X

EON

® P

ROCESSOR

7500 S

ERIES

NCORE

ROGRAMMING

UIDE

UNCORE PERFORMANCE MONITORING

2-101

Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register – Field Definitions

The M-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry

out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by

preloading a monitor with a count value of (2

- 1) - N and setting the control register to send a PMI to

the U-Box. Upon receipt of the PMI, the U-Box will disable counting (

Section 2.1.1.1, “Freezing on

Counter Overflow”

). During the interval of time between overflow and global disable, the counter value

will wrap and continue to collect events.

In this way, software can capture the precise number of events that occurred between the time uncore

counting was enabled and when it was disabled (or ‘frozen’) with minimal skew.

If accessible, software can continuously read the data registers without disabling event collection.

Table 2-68. M_MSR_PMU_CNT_{5-0} Register – Field Definitions

The M-Box also includes a 16b timestamp unit that is incremented each M-Box clock tick. It is a free-

running counter unattached to the rest of the M-Box PMU, meaning it does not generate an event fed to

the other counters.

Field

Bits

Reset

Val

Description

Read zero; writes ignored. (?)

rsv

62:61

Reserved; Must write to 0 else behavior is undefined.

60:25

Read zero; writes ignored. (?)

rsv

24:22

Reserved; Must write to 0 else behavior is undefined.

set_flag_sel

21:19

Selects the ‘set’ condition for enable flag. Secondary event select.

See

Table 2-84, “Performance Monitor Events for M-Box Events”

for

events elected by this field.

NOTE:

Bit 7 (flag_mode) must be set to 1 to enable this field.

rsv

18:14

Reserved; Must write to 0 else behavior is undefined.

inc_sel

13:9

Selects increment signal for this counter. Primary event select.

See

Table 2-84, “Performance Monitor Events for M-Box Events”

for

events elected by this field.

rsv

Reserved; Must write to 0 else behavior is undefined.

flag_mode

Enable conditional counting using set_flag_sel

wrap_mode

Counter wrap mode. If set to 0, this counter will stop counting on

detection of over/underflow. If set to 1, this counter will wrap and

continue counting on detection of over/underflow.

storage_mode

5:4

Storage mode. If set to 0, no count enable flag is required. If set to 1,

count enable flag must have a value of 1 for counting to occur.

count_mode

3:2

00 - count will increase (up)

01 - count will decrease (dn)

10 - count can increase

and

decrease

pmi_en

Enable PMON interrupt on counter over/underflow.

Enable counting

Field

Bits

Reset

Val

Description

event_count

47:0

48-bit performance event counter