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Intel BX80571E7500 Programming Manual - Page 10

Uncore PMU Summary Tables

UPC - 735858206969

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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE INTRODUCTION The general performance monitoring capabilities in each box are outlined in the following table. 1.3 Box C-Box S-Box B-Box M-Box R-Box U-Box W-Box Table 1-1. Per-Box Performance Monitoring Capabilities # Boxes # Counters/ Generic Packet Match/ Box Counters? Mask Filters? Bit Width 8 6 Y N 48 2 4 Y Y 48 2 4 N Y 48 2 6 N N 48 1 (L/R sides) 16 N (2 per port, 8 per side) Y 48 1 1 Y N 48 1 4 Y N 48 Uncore PMU Summary Tables Box R-Box Counters R-Box R R-Box L C-Box Counters C-Box 7 C-Box 3 C-Box 5 C-Box 1 C-Box 6 C-Box 2 C-Box 4 C-Box 0 M-Box Counters Table 1-2. Uncore Performance Monitoring MSRs MSR Addresses Description 0xE3F-0xE30 Counter/Config Registers(15-8) 0xE2F-0xE2C QLX SubConfig Registers for Ports 7-4 0xE2B-0xE24 IPERF 1 SubConfig Registers 0xE22-0xE20 Global (Control/Status/Ovf Control) 0xE1F-0xE10 Counter/Config Registers(7-0) 0xE0F-0xE0C QLX SubConfig Registers for Ports 3-0 0xE0B-0xE04 IPERF 0 SubConfig Registers 0xE02-0xE00 Global (Control/Status/Ovf Control) 0xDFB-0xDF0 Counter/Config Registers 0xDE2-0xDE0 Global (Control/Status/Ovf Control) 0xDDB-0xDD0 Counter/Config Registers 0xDC2-0xDC0 Global (Control/Status/Ovf Control) 0xDBB-0xDB0 Counter/Config Registers 0xDA2-0xDA0 Global (Control/Status/Ovf Control) 0xD9B-0xD90 Counter/Config Registers 0xD82-0xDE0 Global (Control/Status/Ovf Control) 0xD7B-0xD70 Counter/Config Registers 0xD62-0xD60 Global (Control/Status/Ovf Control) 0xD5B-0xD50 Counter/Config Registers 0xD42-0xD40 Global (Control/Status/Ovf Control) 0xD3B-0xD30 Counter/Config Registers 0xD22-0xD20 Global (Control/Status/Ovf Control) 0xD1B-0xD10 Counter/Config Registers 0xD02-0xD00 Global (Control/Status/Ovf Control) 1-2

Section	Page
CHAPTER 1 INTRODUCTION	9
1.1 INTRODUCTION	9
1.2 Uncore PMU Overview	9
1.3 Uncore PMU Summary Tables	10
1.4 References	11
CHAPTER 2 UNCORE PERFORMANCE MONITORING	13
2.1 Global Performance Monitoring Control	13
2.1.1 Counter Overflow	13
2.1.1.1 Freezing on Counter Overflow	13
2.1.1.2 PMI on Counter Overflow	13
2.1.2 Setting up a Monitoring Session	13
2.1.3 Reading the Sample Interval	14
2.1.4 Enabling a New Sample Interval from Frozen Counters	14
2.1.5 Global Performance Monitors	15
2.1.5.1 Global PMON Global Control/Status Registers	15
2.2 U-Box Performance Monitoring	17
2.2.1 U-Box PMON Summary	17
2.2.1.1 U-Box Box Level PMON State	17
2.2.1.2 U-Box PMON state - Counter/Control Pairs	17
2.2.2 U-Box Performance Monitoring Events	18
2.2.3 U-Box Events Ordered By Code	18
2.2.4 U-Box Performance Monitor Event List	19
2.3 C-Box Performance Monitoring	21
2.3.1 Overview of the C-Box	21
2.3.2 C-Box Performance Monitoring Overview	21
2.3.2.1 C-Box PMU - Overflow, Freeze and Unfreeze	21
2.3.3 C-BOX Performance Monitors	22
2.3.3.1 C-Box Box Level PMON state	25
2.3.3.2 C-Box PMON state - Counter/Control Pairs	26
2.3.4 C-BOX Performance Monitoring Events	28
2.3.4.1 An Overview:	28
2.3.4.2 Acronyms frequently used in C-Box Events:	28
2.3.4.3 The Queues:	29
2.3.4.4 Detecting Performance Problems in the C-Box Pipeline:	29
2.3.5 C-Box Events Ordered By Code	29
2.3.6 C-Box Performance Monitor Event List	30
2.4 B-Box Performance Monitoring	41
2.4.1 Overview of the B-Box	41
2.4.2 B-Box Performance Monitoring Overview	41
2.4.2.1 B-Box PMU - On Overflow and the Consequences (PMI/Freeze)	41
2.4.3 B-BOX Performance Monitors	42
2.4.3.1 B-Box Box Level PMON state	42
2.4.3.2 B-Box PMON state - Counter/Control Pairs + Filters	43
2.4.4 B-Box Performance Monitoring Events	45
2.4.4.1 On the ARBQ:	45
2.4.4.2 On the Major B-Box Structures:	46
2.4.4.3 On InvItoE Transactions:	46
2.4.5 B-Box Events Ordered By Code	46
2.4.6 B-Box Performance Monitor Event List	48
2.5 S-Box Performance Monitoring	57
2.5.1 Overview of the S-Box	57
2.5.2 S-Box Performance Monitoring Overview	57
2.5.2.1 S-Box PMU - Overflow, Freeze and Unfreeze	57
2.5.3 S-BOX Performance Monitors	57
2.5.3.1 S-Box PMON for Global State	58
2.5.3.2 S-Box Box Level PMON state	59
2.5.3.3 S-Box PMON state - Counter/Control Pairs + Filters	60
2.5.3.4 S-Box Registers for Mask/Match Facility	61
2.5.4 S-BOX Performance Monitoring Events	63
2.5.4.1 An Overview	63
2.5.4.2 On Queue Occupancy Usage	63
2.5.4.3 On Packet Transmission Events	64
2.5.5 S-Box Events Ordered By Code	65
2.5.6 S-Box Performance Monitor Event List	67
2.6 R-Box Performance Monitoring	84
2.6.1 Overview of the R-Box	84
2.6.1.1 R-Box Input Port	84
2.6.1.2 R-Box Arbitration Control	84
2.6.1.3 R-Box Output Port	85
2.6.1.4 R-Box Link Layer Resources	85
2.6.2 R-Box Performance Monitoring Overview	85
2.6.2.1 Choosing An Event To Monitor - Example	85
2.6.2.2 R-Box PMU - Overflow, Freeze and Unfreeze	86
2.6.3 R-BOX Performance Monitors	86
2.6.3.1 R-Box Performance Monitors To Port Mapping	89
2.6.3.2 R-Box Box Level PMON state	90
2.6.3.3 R-Box PMON state - Counter/Control Pairs + Filters	90
2.6.3.4 R-Box IPERF Performance Monitoring Control Registers	94
2.6.3.5 R-Box QLX Performance Monitoring Control Registers	95
2.6.3.6 R-Box Registers for Mask/Match Facility	96
2.6.4 R-BOX Performance Monitoring Events	99
2.6.4.1 An Overview:	99
2.6.5 R-Box Events Ordered By Code	99
2.6.6 R-Box Performance Monitor Event List	100
2.7 M-Box Performance Monitoring	107
2.7.1 Overview of the M-Box	107
2.7.2 Functional Overview	107
2.7.2.1 Intel ® 7500 Scalable Memory Buffer	108
2.7.3 M-Box Performance Monitoring Overview	108
2.7.3.1 Choosing An Event To Monitor - Example using subcontrol registers	108
2.7.3.2 M-Box PMU - Overflow, Freeze and Unfreeze	109
2.7.4 M-BOX Performance Monitors	110
2.7.4.1 M-Box Box Level PMON state	111
2.7.4.2 M-Box PMON state - Counter/Control Pairs	112
2.7.4.3 M-Box PMU Filter Registers	114
2.7.4.4 M-Box PMU Subcontrol Registers - Subunit descriptions	114
2.7.5 M-Box Performance Monitoring Events	121
2.7.5.1 An Overview:	121
2.7.6 M-Box Events Ordered By Code	122
2.7.7 M-Box Performance Monitor Event List	123
2.8 W-Box Performance Monitoring	136
2.8.1 Overview of the W-Box	136
2.8.2 W-Box Performance Monitoring Overview	136
2.8.2.1 W-Box PMU - Overflow, Freeze and Unfreeze	136
2.8.3 W-BOX Performance Monitors	137
2.8.3.1 W-Box Box Level PMON state	137
2.8.3.2 W-Box PMON state - Counter/Control Pairs	138
2.8.4 W-BOX Performance Monitoring Events	140
2.8.4.1 An Overview:	140
2.8.5 W-Box Events Ordered By Code	140
2.8.6 W-Box Performance Monitor Event List	140

Match case Limit results 1 per page

NTEL

® X

EON

® P

ROCESSOR

7500 S

ERIES

NCORE

ROGRAMMING

UIDE

INTRODUCTION

1-2

The general performance monitoring capabilities in each box are outlined in the following table.

1.3

Uncore PMU Summary Tables

Table 1-1. Per-Box Performance Monitoring Capabilities

Box

# Boxes

# Counters/

Box

Generic

Counters?

Packet Match/

Mask Filters?

Bit Width

C-Box

S-Box

B-Box

M-Box

R-Box

1 (L/R sides)

(2 per port, 8

per side)

U-Box

W-Box

Table 1-2. Uncore Performance Monitoring MSRs

Box

MSR Addresses

Description

R-Box Counters

R-Box R

0xE3F-0xE30

Counter/Config Registers(15-8)

0xE2F-0xE2C

QLX SubConfig Registers for Ports 7-4

0xE2B-0xE24

IPERF 1 SubConfig Registers

0xE22-0xE20

Global (Control/Status/Ovf Control)

R-Box L

0xE1F-0xE10

Counter/Config Registers(7-0)

0xE0F-0xE0C

QLX SubConfig Registers for Ports 3-0

0xE0B-0xE04

IPERF 0 SubConfig Registers

0xE02-0xE00

Global (Control/Status/Ovf Control)

C-Box Counters

C-Box 7

0xDFB-0xDF0

Counter/Config Registers

0xDE2-0xDE0

Global (Control/Status/Ovf Control)

C-Box 3

0xDDB-0xDD0

Counter/Config Registers

0xDC2-0xDC0

Global (Control/Status/Ovf Control)

C-Box 5

0xDBB-0xDB0

Counter/Config Registers

0xDA2-0xDA0

Global (Control/Status/Ovf Control)

C-Box 1

0xD9B-0xD90

Counter/Config Registers

0xD82-0xDE0

Global (Control/Status/Ovf Control)

C-Box 6

0xD7B-0xD70

Counter/Config Registers

0xD62-0xD60

Global (Control/Status/Ovf Control)

C-Box 2

0xD5B-0xD50

Counter/Config Registers

0xD42-0xD40

Global (Control/Status/Ovf Control)

C-Box 4

0xD3B-0xD30

Counter/Config Registers

0xD22-0xD20

Global (Control/Status/Ovf Control)

C-Box 0

0xD1B-0xD10

Counter/Config Registers

0xD02-0xD00

Global (Control/Status/Ovf Control)

M-Box Counters