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Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register - Field Definitions, Table 2-81. M_MSR_PMU_ZDP_CTL_FVC. - specs

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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register - Field Definitions Field ig pbox_init_err evnt3 evnt2 evnt1 evnt0 resp bcmd fvid Bits HW Reset Val Reset Type 31:24 23 22:20 19:17 16:14 13:11 10:8 7:5 4:0 Reads 0; writes ignored. 0 Extension of event select encoding 0b111 (smi_nb_trig). If event select is set to 111 and this bit is set to 1, PBOX reset time events will be counted. 0 FVC Subevent 3 selection. See Table 2-81, "M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings" 0 FVC Subevent 2 selection. See Table 2-81, "M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings" 0 FVC Subevent 1 selection. See Table 2-81, "M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings" 0 FVC Subevent 0 selection. See Table 2-81, "M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings" 0 B-Box response to match on. See Table 2-82, "M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings" 0 B-Box command to match on. See Table 2-82, "M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings" 0 FVID to match on Table 2-81. M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings Name smi_nb_trig resp_match bcmd_match fast_rst alrt_frm psn_txn mem_ecc_err smi_crc_err Value Description 0b111 Select Intel SMI Northbound debug event bits from the Intel SMI status frames as returned from the Intel 7500 Scalable Memory Buffers OR PBOX init error (see pbox_init_err field). These bits are denoted NBDE in the Intel SMI spec status frame description. An OR of all the bits over all the Intel 7500 Scalable Memory Buffers is selected here as an event. NB debug events generate multiple triggers for single NBDE event. Instead, the following triggers listed in M_CCSR_MSC_TRIG_SEL reg must be used: Trigger 51: = Ch1 NBDE Trigger 58 := Ch0 NBDE 0b110 Use response match as programmed by Z_CSR_PMU_ZDP_CTL_FVC.resp to generate trigger. 0b101 Use B-Box command match as programmed by Z_CSR_PMU_ZDP_CTL_FVC.bcmd to generate trigger. 0b100 Fast reset request from MBOS 0b011 An alert frame was detected. 0b010 A write to memory was poisoned. 0b001 Memory ECC error detected (that is not a link-level CRC error). 0b000 Link level Intel SMI CRC error detected. 2-108

Section	Page
CHAPTER 1 INTRODUCTION	9
1.1 INTRODUCTION	9
1.2 Uncore PMU Overview	9
1.3 Uncore PMU Summary Tables	10
1.4 References	11
CHAPTER 2 UNCORE PERFORMANCE MONITORING	13
2.1 Global Performance Monitoring Control	13
2.1.1 Counter Overflow	13
2.1.1.1 Freezing on Counter Overflow	13
2.1.1.2 PMI on Counter Overflow	13
2.1.2 Setting up a Monitoring Session	13
2.1.3 Reading the Sample Interval	14
2.1.4 Enabling a New Sample Interval from Frozen Counters	14
2.1.5 Global Performance Monitors	15
2.1.5.1 Global PMON Global Control/Status Registers	15
2.2 U-Box Performance Monitoring	17
2.2.1 U-Box PMON Summary	17
2.2.1.1 U-Box Box Level PMON State	17
2.2.1.2 U-Box PMON state - Counter/Control Pairs	17
2.2.2 U-Box Performance Monitoring Events	18
2.2.3 U-Box Events Ordered By Code	18
2.2.4 U-Box Performance Monitor Event List	19
2.3 C-Box Performance Monitoring	21
2.3.1 Overview of the C-Box	21
2.3.2 C-Box Performance Monitoring Overview	21
2.3.2.1 C-Box PMU - Overflow, Freeze and Unfreeze	21
2.3.3 C-BOX Performance Monitors	22
2.3.3.1 C-Box Box Level PMON state	25
2.3.3.2 C-Box PMON state - Counter/Control Pairs	26
2.3.4 C-BOX Performance Monitoring Events	28
2.3.4.1 An Overview:	28
2.3.4.2 Acronyms frequently used in C-Box Events:	28
2.3.4.3 The Queues:	29
2.3.4.4 Detecting Performance Problems in the C-Box Pipeline:	29
2.3.5 C-Box Events Ordered By Code	29
2.3.6 C-Box Performance Monitor Event List	30
2.4 B-Box Performance Monitoring	41
2.4.1 Overview of the B-Box	41
2.4.2 B-Box Performance Monitoring Overview	41
2.4.2.1 B-Box PMU - On Overflow and the Consequences (PMI/Freeze)	41
2.4.3 B-BOX Performance Monitors	42
2.4.3.1 B-Box Box Level PMON state	42
2.4.3.2 B-Box PMON state - Counter/Control Pairs + Filters	43
2.4.4 B-Box Performance Monitoring Events	45
2.4.4.1 On the ARBQ:	45
2.4.4.2 On the Major B-Box Structures:	46
2.4.4.3 On InvItoE Transactions:	46
2.4.5 B-Box Events Ordered By Code	46
2.4.6 B-Box Performance Monitor Event List	48
2.5 S-Box Performance Monitoring	57
2.5.1 Overview of the S-Box	57
2.5.2 S-Box Performance Monitoring Overview	57
2.5.2.1 S-Box PMU - Overflow, Freeze and Unfreeze	57
2.5.3 S-BOX Performance Monitors	57
2.5.3.1 S-Box PMON for Global State	58
2.5.3.2 S-Box Box Level PMON state	59
2.5.3.3 S-Box PMON state - Counter/Control Pairs + Filters	60
2.5.3.4 S-Box Registers for Mask/Match Facility	61
2.5.4 S-BOX Performance Monitoring Events	63
2.5.4.1 An Overview	63
2.5.4.2 On Queue Occupancy Usage	63
2.5.4.3 On Packet Transmission Events	64
2.5.5 S-Box Events Ordered By Code	65
2.5.6 S-Box Performance Monitor Event List	67
2.6 R-Box Performance Monitoring	84
2.6.1 Overview of the R-Box	84
2.6.1.1 R-Box Input Port	84
2.6.1.2 R-Box Arbitration Control	84
2.6.1.3 R-Box Output Port	85
2.6.1.4 R-Box Link Layer Resources	85
2.6.2 R-Box Performance Monitoring Overview	85
2.6.2.1 Choosing An Event To Monitor - Example	85
2.6.2.2 R-Box PMU - Overflow, Freeze and Unfreeze	86
2.6.3 R-BOX Performance Monitors	86
2.6.3.1 R-Box Performance Monitors To Port Mapping	89
2.6.3.2 R-Box Box Level PMON state	90
2.6.3.3 R-Box PMON state - Counter/Control Pairs + Filters	90
2.6.3.4 R-Box IPERF Performance Monitoring Control Registers	94
2.6.3.5 R-Box QLX Performance Monitoring Control Registers	95
2.6.3.6 R-Box Registers for Mask/Match Facility	96
2.6.4 R-BOX Performance Monitoring Events	99
2.6.4.1 An Overview:	99
2.6.5 R-Box Events Ordered By Code	99
2.6.6 R-Box Performance Monitor Event List	100
2.7 M-Box Performance Monitoring	107
2.7.1 Overview of the M-Box	107
2.7.2 Functional Overview	107
2.7.2.1 Intel ® 7500 Scalable Memory Buffer	108
2.7.3 M-Box Performance Monitoring Overview	108
2.7.3.1 Choosing An Event To Monitor - Example using subcontrol registers	108
2.7.3.2 M-Box PMU - Overflow, Freeze and Unfreeze	109
2.7.4 M-BOX Performance Monitors	110
2.7.4.1 M-Box Box Level PMON state	111
2.7.4.2 M-Box PMON state - Counter/Control Pairs	112
2.7.4.3 M-Box PMU Filter Registers	114
2.7.4.4 M-Box PMU Subcontrol Registers - Subunit descriptions	114
2.7.5 M-Box Performance Monitoring Events	121
2.7.5.1 An Overview:	121
2.7.6 M-Box Events Ordered By Code	122
2.7.7 M-Box Performance Monitor Event List	123
2.8 W-Box Performance Monitoring	136
2.8.1 Overview of the W-Box	136
2.8.2 W-Box Performance Monitoring Overview	136
2.8.2.1 W-Box PMU - Overflow, Freeze and Unfreeze	136
2.8.3 W-BOX Performance Monitors	137
2.8.3.1 W-Box Box Level PMON state	137
2.8.3.2 W-Box PMON state - Counter/Control Pairs	138
2.8.4 W-BOX Performance Monitoring Events	140
2.8.4.1 An Overview:	140
2.8.5 W-Box Events Ordered By Code	140
2.8.6 W-Box Performance Monitor Event List	140

Match case Limit results 1 per page

NTEL

® X

EON

® P

ROCESSOR

7500 S

ERIES

NCORE

ROGRAMMING

UIDE

UNCORE PERFORMANCE MONITORING

2-108

Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register – Field Definitions

Table 2-81. M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings

Field

Bits

Reset

Val

Reset Type

31:24

Reads 0; writes ignored.

pbox_init_err

Extension of event select encoding 0b111 (smi_nb_trig). If event select

is set to 111 and this bit is set to 1, PBOX reset time events will be

counted.

evnt3

22:20

FVC Subevent 3 selection. See

Table 2-81,

“M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings”

evnt2

19:17

FVC Subevent 2 selection. See

Table 2-81,

“M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings”

evnt1

16:14

FVC Subevent 1 selection. See

Table 2-81,

“M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings”

evnt0

13:11

FVC Subevent 0 selection. See

Table 2-81,

“M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings”

resp

10:8

B-Box response to match on. See

Table 2-82,

“M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings”

bcmd

7:5

B-Box command to match on. See

Table 2-82,

“M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings”

fvid

4:0

FVID to match on

Name

Value

Description

smi_nb_trig

0b111

Select Intel SMI Northbound debug event bits from the Intel SMI

status frames as returned from the Intel 7500 Scalable Memory

Buffers OR PBOX init error (see pbox_init_err field). These bits

are denoted NBDE in the Intel SMI spec status frame description.

An OR of all the bits over all the Intel 7500 Scalable Memory

Buffers is selected here as an event.

NB debug events generate multiple triggers for single NBDE

event. Instead, the following triggers listed in

M_CCSR_MSC_TRIG_SEL reg must be used:

Trigger 51: = Ch1 NBDE

Trigger 58 := Ch0 NBDE

resp_match

0b110

Use response match as programmed by

Z_CSR_PMU_ZDP_CTL_FVC.resp to generate trigger.

bcmd_match

0b101

Use B-Box command match as programmed by

Z_CSR_PMU_ZDP_CTL_FVC.bcmd to generate trigger.

fast_rst

0b100

Fast reset request from MBOS

alrt_frm

0b011

An alert frame was detected.

psn_txn

0b010

A write to memory was poisoned.

mem_ecc_err

0b001

Memory ECC error detected (that is not a link-level CRC error).

smi_crc_err

0b000

Link level Intel SMI CRC error detected.