Intel T8300 Specifications - Page 46

Errata AZ59. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing the stack frame. Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame. Workaround: Software should not generate misaligned stack frames for use with IRET. Status: For the steppings affected, see the Summary Tables of Changes. AZ60. Thermal Interrupts are Dropped During and While Exiting Intel® Deep Power-Down State Problem: Thermal interrupts are ignored while the processor is in Intel Deep Power-Down State as well as during a small window of time while exiting from Intel Deep Power-Down State. During this window, if the PROCHOT signal is driven or the internal value of the sensor reaches the programmed thermal trip point, then the associated thermal interrupt may be lost. Implication: In the event of a thermal event while a processor is waking up from Intel Deep PowerDown State, the processor will initiate an appropriate throttle response. However, the associated thermal interrupt generated may be lost. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 46 Specification Update