Intel T8300 Specifications - Page 27

Errata AZ15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A section "Out-of-Order Stores for String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data size or may observe memory ordering violations. Implication: Upon crossing the page boundary the following may occur, dependent on the new page memory type:  UC the data size of each write will now always be 8 bytes, as opposed to the original data size.  WP the data size of each write will now always be 8 bytes, as opposed to the original data size and there may be a memory ordering violation.  WT there may be a memory ordering violation. Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC, WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled. Status: For the steppings affected, see the Summary Tables of Changes. AZ16. Upper 32 bits of "From" Address Reported through BTMs or BTSs May Be Incorrect Problem: When a far transfer switches the processor from 32-bit mode to IA-32e mode, the upper 32 bits of the "From" (source) addresses reported through the BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may be incorrect. Implication: The upper 32 bits of the 'From' address debug information reported through BTMs or BTSs may be incorrect during this transition. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 27