Intel T8300 Specifications - Page 28

Store Ordering May be Incorrect between WC and WP Memory Type

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Errata AZ17. Address Reported by Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May Be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in the MCA address register (MCi_ADDR). Under some scenarios, the address reported may be incorrect. Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC errors. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AZ18. Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume from System Management Mode) returns to execution flow that results in a Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher priority Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), etc.) Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AZ19. Store Ordering May be Incorrect between WC and WP Memory Type Problem: According to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do. Due to this erratum, WP stores may not drain the WC buffers. Implication: Memory ordering may be violated between WC and WP stores. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 28 Specification Update

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Errata
28
Specification Update
AZ17.
Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May Be Incorrect
Problem:
When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in
the MCA address register (MCi_ADDR). Under some scenarios, the address reported may
be incorrect.
Implication:
Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC
errors.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AZ18.
Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions
Problem:
Normally, when the processor encounters a Segment Limit or Canonical Fault due to code
execution, a #GP (General Protection Exception) fault is generated after all higher
priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume
from System Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher priority
Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug break (#DB),
Machine Check (#MC), etc.)
Implication:
Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions. Intel has not observed this erratum on any commercially
available software.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AZ19.
Store Ordering May be Incorrect between WC and WP Memory Type
Problem:
According to
Intel® 64 and IA-32 Intel Architecture Software Developer's Manual,
Volume 3A
“Methods of Caching Available”, WP (Write Protected) stores should drain the
WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores
do. Due to this erratum, WP stores may not drain the WC buffers.
Implication:
Memory ordering may be violated between WC and WP stores.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.