Hitachi T7K250 Specifications - Page 39
Signal definitionsPATA model
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6.2 Signal definitions(PATA model) The pin assignments of interface signals are listed as follows: Table 16: Signal definitions PIN SIGNAL I/O Type 01 RESET- I TTL 03 DD7 I/O 3-state 05 DD6 I/O 3-state 07 DD5 I/O 3-state 09 DD4 I/O 3-state 11 DD3 I/O 3-state 13 DD2 I/O 3-state 15 DD1 I/O 3-state 17 DD0 I/O 3-state 19 GND 21 DMARQ O 3-state 23 DIOW-(*) I TTL 25 DIOR-(*) I TTL 27 IORDY-(*) O 3-state 29 DMACK- I TTL 31 INTRQ O 3-state 33 DA1 I TTL 35 DA0 I TTL 37 CS0- I TTL 39 DASP- I/O OD PIN SIGNAL I/O Type 02 GND 04 DD08 I/O 3-state 06 DD09 I/O 3-state 08 DD10 I/O 3-state 10 DD11 I/O 3-state 12 DD12 I/O 3-state 14 DD13 I/O 3-state 16 DD14 I/O 3-state 18 DD15 I/O 3-state (20) Key 22 GND 24 GND 26 GND 28 CSEL I TTL 30 GND 32 34 PDIAG- I/O OD 36 DA02 I TTL 38 CS1- I TTL 40 GND Notes: O designates an output from the drive I designates an input to the drive I/O designates an input/output common OD designates an Open-Drain output The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special functions. These lines change from the conventional to special definitions at the moment the host decides to allow a DMA burst, if the Ultra DMA transfer mode was previously chosen via Set Features. The drive becomes aware of this change upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of DMACK- at the termination of the DMA burst. Deskstar T7K250 Hard Disk Drive Specification 25