Sharp CD-XP7700 Service Manual - Page 49

IC3 VHiLC78683E-1: MP3 Decoder LC78683E 1/2

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CD-XP700/CD-XP7700 IC3 VHiLC78683E-1: MP3 Decoder (LC78683E) (1/2) Pin No. Terminal Name Input/Output Function 1 LRSK 2 ADDATA 3 ADBCK 4 ADLRCK 5 C2FIN 6 TEST1 7 CKIN 8 VSS 9 CKOUT 10 TEST2 11 DVDD1 12 PW 13 SBSY 14 SFSY 15* SBCK 16 AVDD 17 VPRER 18 VCOC 19 VPDO 20 AVSS 21 DVDD2 22 VSS 23 MDATA0 24 MDATA1 25 MDATA2 26 MDATA3 27 MDATA4 28 MDATA5 29 MDATA6 30 MDATA7 31 DVDD3 32 VSS 33 MDATA8 34 MDATA9 35 MDATA10 36 MDATA11 37 MDATA12 38 MDATA13 39 MDATA14 40 MDATA15 41 RASB 42 WEB 43 CASLB 44 CASUB 45 OEB 46* MADRS12 47* MADRS11 48* MADRS10 49* MADRS9 50 MADRS8 Input Output Output Output Input Input Input - Output Input Input Input Input Input Output Input - Input Output - Input - Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input - Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Output Output CD L/R clock input. Audio data output. Audio bit clock output. Audio L/R clock output. CD C2 error flag input. Test input 1. (Must be connected to GND.) System clock (16.9344 MHz) input. GND ground pin. External DF/DAC clock (384Fs) output. Test input 2. (Must be connected to GND.) I/O digital supply pin. CD subcode data serial input. CD subcode block synchronization signal input. CD subcode frame synchronization signal input. CD subcode transfer serial clock output. Analog (PLL) supply. VCO oscillator range set pin. VCO control voltage input. VCO charge pump output. Analog GND ground pin. Internal logic supply pin. GND ground pin. DRAM data bus 0. DRAM data bus 1. DRAM data bus 2. DRAM data bus 3. DRAM data bus 4. DRAM data bus 5. DRAM data bus 6. DRAM data bus 7. I/O digital supply pin. GND ground pin. DRAM data bus 8. DRAM data bus 9. DRAM data bus 10. DRAM data bus 11. DRAM data bus 12. DRAM data bus 13. DRAM data bus 14. DRAM data bus 15. RAS output. (L-active) WE output. (L-active) CAS output. (Lower Byte, L-active) CAS output. (Upper Byte, L-active) OE output (L-active) DRAM address output 12. DRAM address output 11. DRAM address output 10. DRAM address output 9. DRAM address output 8. In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside. - 49 -

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– 49 –
CD-XP700/CD-XP7700
IC3 VHiLC78683E-1: MP3 Decoder (LC78683E) (1/2)
1
LRSK
Input
CD L/R clock input.
2
ADDATA
Output
Audio data output.
3
ADBCK
Output
Audio bit clock output.
4
ADLRCK
Output
Audio L/R clock output.
5
C2FIN
Input
CD C2 error flag input.
6
TEST1
Input
Test input 1. (Must be connected to GND.)
7
CKIN
Input
System clock (16.9344 MHz) input.
8
VSS
—
GND ground pin.
9
CKOUT
Output
External DF/DAC clock (384Fs) output.
10
TEST2
Input
Test input 2. (Must be connected to GND.)
11
DVDD1
Input
I/O digital supply pin.
12
PW
Input
CD subcode data serial input.
13
SBSY
Input
CD subcode block synchronization signal input.
14
SFSY
Input
CD subcode frame synchronization signal input.
15*
SBCK
Output
CD subcode transfer serial clock output.
16
AVDD
Input
Analog (PLL) supply.
17
VPRER
—
VCO oscillator range set pin.
18
VCOC
Input
VCO control voltage input.
19
VPDO
Output
VCO charge pump output.
20
AVSS
—
Analog GND ground pin.
21
DVDD2
Input
Internal logic supply pin.
22
VSS
—
GND ground pin.
23
MDATA0
Input/Output
DRAM data bus 0.
24
MDATA1
Input/Output
DRAM data bus 1.
25
MDATA2
Input/Output
DRAM data bus 2.
26
MDATA3
Input/Output
DRAM data bus 3.
27
MDATA4
Input/Output
DRAM data bus 4.
28
MDATA5
Input/Output
DRAM data bus 5.
29
MDATA6
Input/Output
DRAM data bus 6.
30
MDATA7
Input/Output
DRAM data bus 7.
31
DVDD3
Input
I/O digital supply pin.
32
VSS
—
GND ground pin.
33
MDATA8
Input/Output
DRAM data bus 8.
34
MDATA9
Input/Output
DRAM data bus 9.
35
MDATA10
Input/Output
DRAM data bus 10.
36
MDATA11
Input/Output
DRAM data bus 11.
37
MDATA12
Input/Output
DRAM data bus 12.
38
MDATA13
Input/Output
DRAM data bus 13.
39
MDATA14
Input/Output
DRAM data bus 14.
40
MDATA15
Input/Output
DRAM data bus 15.
41
RASB
Output
RAS output. (L-active)
42
WEB
Output
WE output. (L-active)
43
CASLB
Output
CAS output. (Lower Byte, L-active)
44
CASUB
Output
CAS output. (Upper Byte, L-active)
45
OEB
Output
OE output (L-active)
46*
MADRS12
Output
DRAM address output 12.
47*
MADRS11
Output
DRAM address output 11.
48*
MADRS10
Output
DRAM address output 10.
49*
MADRS9
Output
DRAM address output 9.
50
MADRS8
Output
DRAM address output 8.
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.