Foxconn H55MX-S English Manual. - Page 35

Fox Central Control Unit - manual

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Fox Central Control Unit CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc. Fox Central Control Unit ► CPU Configuration [Press Enter] Help Item Ratio Status: Unlocked (Min:09, Max:23) Ratio Actual Value: 23 Configure CPU. Ratio CMOS Setting [23] Current DRAM Speed :1333MHz DRAM Frequency [Auto] Memory Timing by SPD [Auto] Adjust DRAM Voltage [Disabled] 3 Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults ► CPU Configuration Press to go to relative submenu. ► Ratio CMOS Setting This item is used to set the ratio between CPU Core Clock and the FSB Frequency. You can use [+] or [-] to adjust the value. ► DRAM Frequency This item is used to adjust the memory speed. Select [Auto] for SPD enable mode. You can select a value manually such as [800 MHz], [1067 MHz] and [1333MHz].. ► Memory Timing by SPD This item is used to enable/disable provision of DRAM timing by SPD device. The Serial Presence Detect (SPD) device is a small EEPROM chip, mounted on a memory module. It contains important information about the module's speed, size, addressing mode and various other parameters, so that the motherboard memory controller (chipset) can better access the memory device. Select [Auto] for SPD enable mode. Select [Manual] to set the parameters by yourself. The following 10 settings are valid only when the Memory Timing by SPD is set to [Manual]. ► DRAM tCL The number of memory clocks it takes a DRAM to return data after the read CAS_L is asserted depends on the memory clock frequency. The value that BIOS programs into the memory controller is a function of the target clock frequency. The target clock frequency is determined from the supported CAS latencies at given clock frequencies of each DIMM. ► DRAM tRAS (Active-to-Precharge Delay) This item allows you to set the minimum RAS# active time (in clock cycles). ► DRAM tRP (Precharge Command Period) This item allows you to select the row precharge time (in clock cycles). ► DRAM tRCD (RAS-to-CAS Delay) This item allows you to select a delay time (in clock cycles) between the CAS# and RAS# strobe signals. 28

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28
Fox Central Control Unit
CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc.
Fox Central Control Unit
► CPU Configuration
Help Item
Ratio Status: Unlocked (Min:09, Max:23)
Ratio Actual Value: 23
Ratio CMOS Setting
[23]
Current DRAM Speed
:1333MHz
DRAM Frequency
[Auto]
Memory Timing by SPD
[Auto]
Adjust DRAM Voltage
[Disabled]
↑↓←→:Move
Enter:Select
+/-/:Value
F10:Save
ESC:Exit
F1:General Help
F9:Optimized Defaults
[Press Enter]
Configure CPU.
► CPU Configuration
Press <Enter> to go to relative submenu.
► Ratio CMOS Setting
This item is used to set the ratio between CPU Core Clock and the FSB Frequency. You can
use [+] or [-] to adjust the value.
► DRAM Frequency
This item is used to adjust the memory speed. Select [Auto] for SPD enable mode. You can
select a value manually suc
h as [800 MHz], [1067 MHz] and [1333MHz]..
► Memory Timing by SPD
This item is used to enable/disable provision of DRAM timing by SPD device. The Serial
Presence Detect (SPD) device is a small EEPROM chip, mounted on a memory module. It
contains important information about the module's speed, size, addressing mode and various
other parameters, so that the motherboard memory controller (chipset) can better access the
memory device.
Select [Auto] for SPD enable mode.
Select [Manual] to set the parameters by yourself.
The following 10 settings are valid only when the Memory Timing by SPD is set to [Manual].
► DRAM tCL
The number of memory clocks it takes a DRAM to return data after the read CAS_L is assert-
ed depends on the memory clock frequency. The value that BIOS programs into the memory
controller is a function of the target clock frequency. The target clock frequency is determined
from the supported CAS latencies at given clock frequencies of each DIMM.
► DRAM tRAS (Active-to-Precharge Delay)
This item allows you to set the minimum RAS# active time (in clock cycles).
► DRAM tRP (Precharge Command Period)
This item allows you to select the row precharge time (in clock cycles).
► DRAM tRCD (RAS-to-CAS Delay)
This item allows you to select a delay time (in clock cycles) between the CAS# and RAS#
strobe signals.