Asus RS720A-E11-RS12 User Manual - Page 28

SMU FW Successfully loaded to SMU Secure DRAM, Bootloader successfully loaded SMU FW

Page 28 highlights

Action PSP Boot PHASE PSP Boot Loader phase (Status Post Codes) POST CODE 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF TYPE Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress DESCRIPTION Bootloader successfully entered C Main Master initialized C2P / slave waited for master to init C2P HMAC key successfully derived Master got Boot Mode and sent boot mode to all slaves SpiRom successfully initialized BIOS Directory successfully read from SPI to SRAM Early unlock check Inline Aes key successfully derived Inline-AES key programming is done Inline-AES key wrapper derivation is done Bootloader successfully loaded HW IP configuration values Bootloader successfully programmed MBAT table Bootloader successfully loaded SMU FW PSP and SMU configured WAFL User mode test harness completed successfully Bootloader loaded Agesa0 from SpiRom AGESA phase has completed RunPostDramTrainingTests() completed successfully SMU FW Successfully loaded to SMU Secure DRAM Sent all required boot time messages to SMU Validated and ran Security Gasket binary UMC Keys generated and programmed Inline AES key wrapper stored in DRAM Completed FW Validation step Completed FW Validation step BIOS copy from SPI to DRAM complete Completed FW Validation step BIOS load process fully complete Bootloader successfully release x86 Early Secure Debug completed GetFWVersion command received from BIOS is completed SMIInfo command received from BIOS is completed (continued on the next page) 1-18 Chapter 1: Product Introduction

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Chapter 1: Product Introduction
1-18
Action
PHASE
POST CODE
TYPE
DESCRIPTION
PSP Boot
PSP Boot Loader
phase (Status
Post Codes)
0xA0
Progress
Bootloader successfully entered C Main
0xA1
Progress
Master initialized C2P / slave waited for master to init C2P
0xA2
Progress
HMAC key successfully derived
0xA3
Progress
Master got Boot Mode and sent boot mode to all slaves
0xA4
Progress
SpiRom successfully initialized
0xA5
Progress
BIOS Directory successfully read from SPI to SRAM
0xA6
Progress
Early unlock check
0xA7
Progress
Inline Aes key successfully derived
0xA8
Progress
Inline-AES key programming is done
0xA9
Progress
Inline-AES key wrapper derivation is done
0xAA
Progress
Bootloader successfully loaded HW IP configuration values
0xAB
Progress
Bootloader successfully programmed MBAT table
0xAC
Progress
Bootloader successfully loaded SMU FW
0xAD
Progress
PSP and SMU configured WAFL
0xAE
Progress
User mode test harness completed successfully
0xAF
Progress
Bootloader loaded Agesa0 from SpiRom
0xB0
Progress
AGESA phase has completed
0xB1
Progress
RunPostDramTrainingTests() completed successfully
0xB2
Progress
SMU FW Successfully loaded to SMU Secure DRAM
0xB3
Progress
Sent all required boot time messages to SMU
0xB4
Progress
Validated and ran Security Gasket binary
0xB5
Progress
UMC Keys generated and programmed
0xB6
Progress
Inline AES key wrapper stored in DRAM
0xB7
Progress
Completed FW Validation step
0xB8
Progress
Completed FW Validation step
0xB9
Progress
BIOS copy from SPI to DRAM complete
0xBA
Progress
Completed FW Validation step
0xBB
Progress
BIOS load process fully complete
0xBC
Progress
Bootloader successfully release x86
0xBD
Progress
Early Secure Debug completed
0xBE
Progress
GetFWVersion command received from BIOS is completed
0xBF
Progress
SMIInfo command received from BIOS is completed
(continued on the next page)