Intel SL6NQ Specification Update - Page 24

Summary Table of Changes Errata (Sheet 3 of 4) No. C1/ D0/ B0/ C1/ D1/ M0/ L0/ 0F0Ah 0F12h 0F24h 0F27h 0F29h 0F25h 0F29h Plans Errata P47 X X X X X X X No Fix Re-mapping the APIC base address to a value less than or equal to 0xDC001000 may cause I/O and special cycle failure P48 X X X X X No Fix Erroneous BIST result found in EAX register after reset P49 X X X Fixed Processor does not flag #GP on non-zero write to certain MSRs P50 X X X X X X No Fix Simultaneous assertion of A20M# and INIT# may result in incorrect data fetch P51 X X Fixed Processor does not respond to break requests from ITP P52 X X X Fixed Glitches on address and data strobe signals may cause system shutdown P53 X X X X X X X No Fix A write to an APIC Register Sometimes May Appear to Have Not Occured P54 X X X Plan Fix STPCLK# signal assertion under certain conditions may cause a system hang P55 X X X X Plan Fix Store to load data forwarding may result in switched data bytes P56 X X X X Plan Fix ITP cannot continue single step execution after the first breakpoint P57 X X X X X X X No Fix Parity error in the L1 cache may cause the processor to hang P58 X X X X X X X Plan Fix The TCK input in the test access port (TAP) is sensitive to low clock edge rates and prone to noise coupling onto TCK's rising or falling edges P59 X X X X X X X No Fix Disabling a local APIC disables both logical processor on a Hyper-Threading Technology enabled processor P60 X X X X X X X No Fix Using STPCLK and executing code from very slow memory could lead to a system hang P61 X Plan Fix Simultaneous cache line eviction from L2 and L3 caches may result in the write back of stale data P62 X X X X X X X No Fix The state of the resume flag (RF flag) in a task-state segment (TSS) may be incorrect P63 X X X X No Fix Changes to CR3 register do not fence pending instruction page P64 X X X X X Plan Fix Simultaneous page-faults at similar page offsets on both logical processors of an Hyper-Threading Technology enabled processor may cause application failure P65 X X X X X X X No Fix A 16-bit address wrap resulting from a near branch (jump or call) may cause an incorrect address to be reported to the #GP exception handler P66 X X X X X X X No Fix Locks and SMC detection may cause the processor to temporarily hang P67 X X X X X X X No Fix Incorrect debug exception (#DB) may occur when a data breakpoint is set on a FP instruction 24 Intel® Xeon® Processor Specification Update