Foxconn D42S 3.0 User manual - Page 32

3 access the memory device. Select [Enabled] for SPD enable mode. Select [Disabled] to set the parameters by yourself. The following 4 settings are valid only when the Configure DRAM Timing by SPD is set to [Disabled]. ► DRAM CAS# Latency This item controls the CAS latency. The CAS Latency is the number of clock cycles that elapse from the time the request for data is sent to the actual memory location until the data is transmitted from the module. ► DRAM RAS# to CAS# Delay This item allows you to select a delay time (in clock cycles) between the CAS and RAS strobe signals. ► DRAM RAS# Precharge This item allows you to select the DRAM RAS precharge time (in clock cycles). ► DRAM RAS# Activate to Precharge This item allows you to set the precharge delay time (in clock cycles). CPU Configuration CMOS Setup Utility - Copyright (C) 1985-2010, American Megatrends, Inc. CPU Configuration CPU Configuration Help Item Module Version : 3F.1B When disable, force Manufacturer : Intel the XD feature flay to Intel(R) Atom(TM) CPU D425 @1.80GHz always return 0. Frequency :1.80GHz FSB Speed :800MHz Cache L1 :24KB Cache L2 :512KB Ratio Actual Value:9 Execute-Disable Bit Capabili [Enabled] Hyper Threading Technology [Enabled] Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults ► Execute-Disable Bit Capabili This item is used to enable/disable the Execute Disable Bit feature. Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. Execute Disable Bit allows the processor to classify areas in memory by where application code can execute and where it cannot. When a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage and worm propagation. 25