Asus P12R-M Series User Manual - Page 90
Force to X.X GT/s], PCI Express GEN2 Link Register Settings
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ARI Forwarding [Disabled] If supported by hardware and set to [Enabled], the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type1 Configuration Request into a Type0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. Configuration options: [Disabled] [Enabled] Atomic0p Requester Enable [Disabled] If supported by hardware and set to [Enabled], this function initiates Atomic0p Requests only if Bus Master Enable bit is in the Command Register Set. Configuration options: [Disabled] [Enabled] Atomic0p Egress Blocking [Disabled] If supported by hardware and set to [Enabled], outbound Atomic0p Requests via Egress Ports will be blocked. Configuration options: [Disabled] [Enabled] IDO Request Enable [Disabled] If supported by hardware and set to [Enabled], this permits setting the number of IDBased Ordering (IDO) bit (Attribute[2]) requests to be initiated. Configuration options: [Disabled] [Enabled] IDO Completion Enable [Disabled] If supported by hardware and set to [Enabled], this permits setting the number of IDBased Ordering (IDO) bit (Attribute[2]) requests to be initiated. Configuration options: [Disabled] [Enabled] LTR Mechanism Enable [Disabled] If supported by hardware and set to [Enabled], this enables the Latency Tolerance Reporting (LTR) Mechanism. Configuration options: [Disabled] [Enabled] End-End TLP Prefix Blocking [Disabled] If supported by hardware and set to [Enabled], this function will block forwarding of TLPs containing End-End TLP Prefixes. Configuration options: [Disabled] [Enabled] PCI Express GEN2 Link Register Settings Target Link Speed [Auto] If supported by hardware and set to [Force to X.X GT/s], for Downstream Ports, this sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. When [Auto] is selected HW initialized data will be used. Configuration options: [Disabled] [Force to 2.5 GT/s] [Force to 5.0 GT/s] [Force to 8.0 GT/s] [Force to 16.0 GT/s] [Force to 32.0 GT/s] Clock Power Management [Disabled] If supported by hardware and set to [Enabled], the device is permitted to use CLKREQ# signal for power management of Link clock in accordance to protocol defined in appropriate form factor specification. Configuration options: [Disabled] [Enabled] 4-26 Chapter 4: BIOS Setup