AMD AMD-K6-2/500AFX Data Sheet - Page 71
Write Handling Control Register (WHCR)–Model 8/[F:8], Write Handling, Control Register
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 63 43 210 DS EWBEC P C EE Reserved Symbol Description Bit EWBEC EWBE Control 3-2 DPE Data Prefetch Enable 1 SCE System Call Extension 0 Figure 47. Extended Feature Enable Register (EFER)-Model 8/[F:8] Table 13. Extended Feature Enable Register (EFER)-Model 8/[F:8] Definition Bit Description R/W Function 63-4 Reserved R Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits are always read as 0. This 2-bit field controls the behavior of the processor with 3-2 EWBE Control (EWBEC) R/W respect to the ordering of write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE Disable (GEWBED) and Speculative EWBE Disable (SEWBED), respectively. DPE must be set to 1 to enable data prefetching (this is the default setting following reset). If enabled, cache misses 1 Data Prefetch Enable (DPE) R/W initiated by a memory read within a 32-byte cache line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 System Call Extension (SCE) R/W SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions. For more information on EWBEC, see "EWBE Control" on page 201. Write Handling Control Register (WHC R) - Model 8/[F:8] The Write Handling Control Register (WHCR) is a MSR that contains two fields -the Write Allocate Enable Limit (WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit (see Figure 48). For more information, see "Write Allocate" on page 186. Note: The WHCR register as defined in the Model 8/[7:0] has changed in the Model 8/[F:8]. See "Write Handling Control Register (WHCR)-Model 8/[7:0]" on page 40. Chapter 3 Software Environment 51