Adaptec 1737100 Programmer Manual

Adaptec 1737100 - 62044 SGL ENET PCI 4CH Manual

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  • Adaptec 1737100 | Programmer Manual - Page 1
    Programmer's Manual AIC-6915 Ethernet LAN Controller R Document Title: ABA-1030 DVB Satellite Receiver Stock Number: 512130-00, Rev. A Print Spec Number: 497767-00, Rev. AA Current Date: 10/10/98 Cover-1
  • Adaptec 1737100 | Programmer Manual - Page 2
    , Inc. 691 South Milpitas Boulevard Milpitas, CA 95035 © 1998, Adaptec, Inc. All rights reserved. Adaptec and the Adaptec logo are registered trademarks of Adaptec, Inc. Printed in Singapore STOCK NO: 512130-00, Rev. A SG 9/98 Document Title: ABA-1030 DVB Satellite Receiver Stock Number: 512130
  • Adaptec 1737100 | Programmer Manual - Page 3
    w w w w w AIC-6915 Ethernet LAN Controller Programmer's Manual Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 R Page: Front Matter-i ECN Date: xx/xx/xx
  • Adaptec 1737100 | Programmer Manual - Page 4
    s To use the Adaptec Interactive Support System, call 800-959-7274 or 408-945-2550, 24 hours a day, 7 days a week. The system prompts you with questions regarding your problem and then provides step-by-step troubleshooting instructions. s To speak with a product support representative, call 408-934
  • Adaptec 1737100 | Programmer Manual - Page 5
    Descriptor) 3-9 Type 4, 32-bit Addressing Mode (Frame Descriptor) 3-9 Transmit Completion Queue Entry 3-10 Document Title: AIC-6915 Ethernet LAN Controller Programmer's Manual Stock Number: xxxxxx-xx Rev. x Page: Front Matter-iii iii Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98
  • Adaptec 1737100 | Programmer Manual - Page 6
    AIC-6915 Ethernet LAN Controller Programmer's Manual 4 PCI Module Architecture Features 4-1 PCI Block Diagram 4-3 PCI Master Module 4-4 64 Space 5-3 Internal Registers 5-3 External Registers 5-4 Block Diagram 5-5 Instruction Formats 5-6 6 AIC-6915 Internal Registers Summary PCI Configuration Header
  • Adaptec 1737100 | Programmer Manual - Page 7
    Filtering Registers 7-82 MAC Statistic Registers 7-84 8 Sample Driver Code Conventions 8-1 Producer-Consumer Model for the AIC-6915 Buffer Descriptor Queue 8-17 Document Title: AIC-6915 Ethernet LAN Controller Programmer's Manual Stock Number: xxxxxx-xx Rev. x Page: Front Matter-v Print Spec
  • Adaptec 1737100 | Programmer Manual - Page 8
    AIC-6915 Ethernet LAN Controller Programmer's Manual Transmit Buffer Descriptor Types 8-18 Two Transmit Queues 8-20 Transmit Producer-Consumer Model 8-20 Transmit Initialization 8-21 Transmit Handling 8-25 Transmit Completion Interrupt Handling 8-27
  • Adaptec 1737100 | Programmer Manual - Page 9
    w w w w Figures Figure 1-1 AIC-6915 Block Diagram 1-5 2-1 The AIC-6915 Receive Data Structures 2-2 3-1 Transmit Host Communication Data Structure 3-4 4-1 PCI Block Diagram 4-3 4-2 64-bit PCI Reset Timing 4-5 5-1 Data Processing Unit 5-5 7-1 AIC-6915 PCI Address Map 7-3 Document Title: Document
  • Adaptec 1737100 | Programmer Manual - Page 10
    Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 Page: Front Matter-viii ECN Date: xx/xx/xx
  • Adaptec 1737100 | Programmer Manual - Page 11
    CBE[3:0] Values 4-13 5-1 Status/Control Register 5-3 5-2 Instruction Formats 5-6 6-1 PCI Configuration Header Registers Summary 6-1 6-2 7-9 Subclass Register 7-9 Document Title: AIC-6915 Ethernet LAN Controller Programmer's Manual Stock Number: xxxxxx-xx Rev. x Page: Front Matter-ix ix Print
  • Adaptec 1737100 | Programmer Manual - Page 12
    7-40 TxDescQueueProducerIndex Register 7-40 TxDescQueueConsumerIndex Register 7-41 TxDmaStatus1 Register 7-41 Document Title: AIC-6915 Ethernet LAN Controller Programmer's Manual x Stock Number: xxxxxx-xx Rev. x Page: Front Matter-x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10
  • Adaptec 1737100 | Programmer Manual - Page 13
    7-73 BkToBkIPG Register 7-74 NonBkToBkIPG Register 7-75 ColRetry Register 7-75 MaxLength Register 7-76 Document Title: AIC-6915 Ethernet LAN Controller Programmer's Manual Stock Number: xxxxxx-xx Rev. x Page: Front Matter-xi Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 ECN
  • Adaptec 1737100 | Programmer Manual - Page 14
    Receive Frame Processor Register 7-87 7-112 FifoAccess Register 7-87 8-1 AIC-6915 DDK Features 8-29 Document Title: AIC-6915 Ethernet LAN Controller Programmer's Manual xii Stock Number: xxxxxx-xx Rev. x Page: Front Matter-xii Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 ECN
  • Adaptec 1737100 | Programmer Manual - Page 15
    1 w w w w Introduction The Adaptec AIC-6915, PCI 10/100 Ethernet LAN Controller provides 6915 provides an External Interface port for access to a ROM/EEPROM (for add-in card local BIOS support, or boot ROM) and general purpose registers. A separate 4-wire Serial EEPROM port allows for downloading
  • Adaptec 1737100 | Programmer Manual - Page 16
    LAN Controller Programmer's Manual Features General s Supports four general purpose I/Os that can be programmed separately as inputs, outputs, open-drain outputs or, interrupt inputs s Interface to an external, 8-bit Boot ROM with a maximum size of 256-KByte s Supports dynamic system bus (PCI
  • Adaptec 1737100 | Programmer Manual - Page 17
    Microsoft Device Class Power Management Reference Specification (OnNow) s PC 97 ready. Implements all hardware features required by Microsoft's PC 98 design specification s Supports 3.3V and 5.0V PCI signaling s Direct pin out connection to PCI 32/64-bit bus interface s PCI bus master with zero wait
  • Adaptec 1737100 | Programmer Manual - Page 18
    AIC-6915 Ethernet LAN Controller Programmer's Manual - Memory Write And Invalidate s Supports PCI bus address and data parity generation and checking s Supports PCI PERR and SERR requirements s Supports 8-bit, 256-KByte, external Memory port for interface with external Boot ROM or devices/registers
  • Adaptec 1737100 | Programmer Manual - Page 19
    Introduction Block Diagram Figure 1-1 is a block diagram of the AIC-6915. Status (Receive) MAC (Transmit) Data (8) Status Data (8) Station Address TCP Checksum Wakeup Statistics TxFrame Sync. Status RxFrame Control RxDMA Receive Clock FIFO Bus (32-bits) Arbiter 8 KByte SRAM Combined
  • Adaptec 1737100 | Programmer Manual - Page 20
    AIC-6915 Ethernet LAN Controller Programmer's Manual Modules The AIC-6915 contains the following major modules: s PCI - Controls access to the PCI bus and contains PCI-specific registers. s BusAccessControl - Arbitrates master accesses
  • Adaptec 1737100 | Programmer Manual - Page 21
    of the frame sizes s Each frame requires only 8 bytes of overhead in the FIFO s IEEE 802.3x based flow control s Cisco's ISL frame support (Implemented in the MAC) Additional value-added features s Power management. s Wakeup frames compliant to Microsoft's OnNow specification s TCP and UDP checksum
  • Adaptec 1737100 | Programmer Manual - Page 22
    AIC-6915 Ethernet LAN Controller Programmer's Manual s VLAN support: - Address filtering based on VLAN - Ability to delete VLAN tag and number from frame returned to the host s Optional second buffer list for allocating two
  • Adaptec 1737100 | Programmer Manual - Page 23
    the Valid bit again. s The AIC-6915 does not reset the 'Valid' bit in the descriptor queue. It is the software driver's responsibility to manage the queue. The software driver can do this by maintaining at least one invalid descriptor right after the group of valid ones. s In Polling mode, software
  • Adaptec 1737100 | Programmer Manual - Page 24
    AIC-6915 Ethernet LAN Controller Programmer's Manual 32-bit Addressing Mode Table 2-1. Receive Buffer Descriptor (One- may be 1, 2, or 4 words, depending on the amount of information required by the driver. Only 1 or 2 word completion descriptors may be used if the receive and transmit completion
  • Adaptec 1737100 | Programmer Manual - Page 25
    of bytes in the FIFO exceeds a programmable threshold (RxHighPriorityThreshold), the receive DMA engine is granted priority over the transmit engine for DMA services. Completion Descriptor A completion descriptor is normally DMA-transferred to the host when a good frame is received. The frame is DMA
  • Adaptec 1737100 | Programmer Manual - Page 26
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 2-3. Short (Type 0) Completion Entry 31 24 23 16 15 8 7 0 0 1 Status1 EndIndex Length Table 2-4. Basic (Type 1) Completion Descriptor 31 24 23 16 15 8 7 0 0 1 Status1 EndIndex
  • Adaptec 1737100 | Programmer Manual - Page 27
    Receive Architecture Table 2-7. Receive Completion Descriptor (Word 0) Bit(s) Description/Function Status1 field 29 OK - The frame is good. There were no CRC errors, dribble nibble, illegal lengths, or receive code violations. In ISL mode, the ISL and Ethernet checksums must both be valid. This
  • Adaptec 1737100 | Programmer Manual - Page 28
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 2-8. Receive Completion Descriptor (Word 1) Bit(s) Description/Function Status2 field 31 Perfect - destination address matches one of the 16 predefined "perfect" addresses. 30 Hash - hashed
  • Adaptec 1737100 | Programmer Manual - Page 29
    Receive Architecture Table 2-9. Receive Completion Descriptor (Word 2) Bit(s) Description/Function Partial TCP/UDP checksum field 31:16 Partial TCP/UDP Checksum - When fragmented TCP/UDP frames are received, the partial TCP/UDP checksum of the first frame is calculated by the TCP/UDP header
  • Adaptec 1737100 | Programmer Manual - Page 30
  • Adaptec 1737100 | Programmer Manual - Page 31
    for high-priority packets and one for low-priority packets. s Driver notifies the transmit block to start transmitting packets by writing the " poll host memory for new packets. s Five descriptor types are supported. Descriptors can be categorized as "frame descriptors", which contain multiple
  • Adaptec 1737100 | Programmer Manual - Page 32
    AIC-6915 Ethernet LAN Controller Programmer's Manual s There are three kinds of interrupts generated by the transmit is not enabled until the checksum calculation is finished. For non-TCP/UDP packets, the driver can set the CALTCP bit to zero in the descriptor to disable checksum calculation and the
  • Adaptec 1737100 | Programmer Manual - Page 33
    in a local register file. When the mode of "Transmit Complete Interrupt" is on, the transmit status is DMA-transferred to the host. s 64-bit addressing support on all data buffers. The "Descriptor Queue" and the "Completion Queue" are also 64-bit addressing, but they share the same high-order 32-bit
  • Adaptec 1737100 | Programmer Manual - Page 34
    AIC-6915 Ethernet LAN Controller Programmer's Manual Transmit Data Structure Figure 3-1 illustrates the Transmit Data Structure Buffer Descriptors for Hi-Priority Skip Field Frame Header Pkt 1 Buf1 Pkt 1 Buf2 Pkt 1 Buf3 Skip
  • Adaptec 1737100 | Programmer Manual - Page 35
    following sections. Both high-priority and low-priority queues have base addresses aligned on a 256-byte boundary. Five descriptor types are supported. The driver must program the descriptor type during initialization. Descriptors are in multiples of 8-bytes. The Descriptor Queue is aligned on a 256
  • Adaptec 1737100 | Programmer Manual - Page 36
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 3-1. Type 0 Transmit DMA Descriptor (32-bit Addressing Only) 31 24 32 16 15 8 7 0 Skip Field (multiple of 8 bytes) One Skip Field per Packet ID = 4'
  • Adaptec 1737100 | Programmer Manual - Page 37
    None of the two interrupt status bits is set. 1 1 TxFrameCompleteInt is set after complete transmitting the whole frame. 'INTR' Note: The software driver may choose to work with another interrupt status bit, TxQueueDoneInt, that is not controlled by 'INTR'. The AIC-6915 sets this bit after the
  • Adaptec 1737100 | Programmer Manual - Page 38
    AIC-6915 Ethernet LAN Controller Programmer's Manual s Total Packet Length: This 16-bit field defines frame only. The ID, Length, and Address are valid for all buffers of the frame. The software driver must use the 'End' bit only in the first buffer descriptor of a frame. The queue wraps around
  • Adaptec 1737100 | Programmer Manual - Page 39
    High Address Length (bytes) Type 3, 32-bit Addressing Mode (Frame Descriptor) This mode is currently not supported in the AIC-6915. Type 4, 32-bit Addressing Mode (Frame Descriptor) Type 4 enables the driver to execute a simple and fast copy of DOS and OS2 data structure (given by the upper layer
  • Adaptec 1737100 | Programmer Manual - Page 40
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 3-6. Type 4 Transmit DMA Descriptor (32-bit Addressing only) 31 24 23 16 15 8 7 0 Skip Field (multiple of 8 bytes) One Skip Field per Packet ID = 4'
  • Adaptec 1737100 | Programmer Manual - Page 41
    Transmit Architecture If the AIC-6915 is programmed to transmit two words (8 bytes), the second word (bit 6332) is the InterruptStatus register content. Table 3-8. Transmit Completion Queue Entry Type = Transmit Complete Entry 31 29 28 16 15 14 0 Type Transmit Status Pr i Index s Type -3
  • Adaptec 1737100 | Programmer Manual - Page 42
  • Adaptec 1737100 | Programmer Manual - Page 43
    Microsoft Device Class Power Management Reference Specification (OnNow) s PC 97 ready. Implements all hardware features required by Microsoft's PC 97 design specification s Supports 3.3V and 5.0V PCI signaling s Direct pin out connection to PCI 32/64-bit bus interface s PCI bus master with zero wait
  • Adaptec 1737100 | Programmer Manual - Page 44
    LAN Controller Programmer's Manual s Supports PCI PERR and SERR requirements. s Supports 8-bit, 256-KByte, external Memory port for interface with external Boot ROM or devices/registers. s Supports external Boot ROM access from memory or Expansion ROM address space. s Supports an external I2C
  • Adaptec 1737100 | Programmer Manual - Page 45
    PCI Block Diagram Figure 4-1 is a PCI block diagram. PCI_PADS PCI_TOP PCI Module Architecture PCI Module BUFOUTFLOPS/OUTFLOPS PCIMST Pcimaster Logic PCITGT TGTDPU Datapath Logic TGTCTL control logic BAC Bus Access Control DECODER Address Decoder EEPROMCNTL Serial EPROM BOOTROMCTL Memory Port
  • Adaptec 1737100 | Programmer Manual - Page 46
    Manual systems where reading extra bytes might cause a problem. The PCI master module samples DEVSEL_ when if a parity error is detected. The software driver can request the AIC-6915 to stop the suspend any other DMA operations until the error is serviced. The PCI master is designed to burst data
  • Adaptec 1737100 | Programmer Manual - Page 47
    -6915 restarts the transaction with a 32-bit transfer. Under this situation, it is very possible that the target is a 32-bit device and does not support multiple-data transfer cycles. If the master continues with the 64-bit data transfer cycle, the lower 32-bit data byte enables are deasserted and
  • Adaptec 1737100 | Programmer Manual - Page 48
    AIC-6915 Ethernet LAN Controller Programmer's Manual Arbitration The AIC-6915 drives AD[31:00] during 32-bit transfers and AD[63:0] during 64-bit transfers. CBE[3:0]_ are asserted on the first
  • Adaptec 1737100 | Programmer Manual - Page 49
    s Sub Class [7:0] s Base Class [7:0] s SubSystem Vendor ID [7:0] s SubSystem Vendor ID [15:8] s SubSystem Device ID [7:0] s SubSystem Device ID [15:8] s Interrupt Pin [7:0] The target does not support data bursts. Rather it disconnects after the first Data phase. In addition, the AIC-6915 does not
  • Adaptec 1737100 | Programmer Manual - Page 50
    AIC-6915 Ethernet LAN Controller Programmer's Manual Power Management The PCI bus power management defined four power states. D0 indicates the "On" state, D3 indicates the "Off" state, and D1 and D2 represent power managed states. In the AIC-6915, three states are supported. D0 and D3 are required
  • Adaptec 1737100 | Programmer Manual - Page 51
    32-bit bus mastering capability. The CardBus interface is based on the PCI interface with lower power consumption, additional signals and registers supported. There are four 32-bit CardBus registers. The following events must be implemented: s Function Event s Function Event Mask s Function Present
  • Adaptec 1737100 | Programmer Manual - Page 52
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 4-2 lists all 16 PCI commands and the received MRDC with an address equal to the one stored in IndirectIoAddress. I/O Write IOWR Supports IOWR to the IndirectIoDataPort and IndirectIoAddress registers. When writing to the Data port, the
  • Adaptec 1737100 | Programmer Manual - Page 53
    ] = 0H and FRAME_ to validate the Configuration register address decode. The AIC-6915 then asserts DEVSEL_ to claim the transaction. The AIC-6915 supports a read/write operation to its configuration space with any combination of CBE[3:0]_ as defined in the PCI specification. For a read, the AIC-6915
  • Adaptec 1737100 | Programmer Manual - Page 54
    AIC-6915 Ethernet LAN Controller Programmer's Manual Expansion ROM Address Space When in target mode, all the data is available and ready in the memory interface module. The AIC-6915 does not support writes to expansion ROM space. Memory Address Space The AIC-6915 uses Base Address 0 to request
  • Adaptec 1737100 | Programmer Manual - Page 55
    describes how the AIC-6915 responds to different commands. Table 4-3. Address Phase CBE[3:0] Values Command CBE [3:0]_ Abbrev. Type AIC-6915 Support Target Master 0000 IAC Interrupt Acknowledge No No 0001 SSC Special Cycle No No 0010 0011 IORDC IOWRC I/O Read I/O Write Yes No
  • Adaptec 1737100 | Programmer Manual - Page 56
    AIC-6915 Ethernet LAN Controller Programmer's Manual Illegal Behavior As a target, when the AIC-6915 accepts a cycle (I/O, memory, configuration) which is addressed to it and drives DEVSEL_, it checks the legality of
  • Adaptec 1737100 | Programmer Manual - Page 57
    the receive block does not take advantage of that option (REQNEXTDATA is asserted all the time) and assumes that there are at list three instructions the processor can execute between two consecutive assertions of DATAVALID. In the interface with the transmit DMA engine, a 64-bit doubleword is read
  • Adaptec 1737100 | Programmer Manual - Page 58
    AIC-6915 Ethernet LAN Controller Programmer's Manual s LC= 0, 1 or 2, and EXCONCLOCK is set, or s Read/Write instruction is executed and the Input IOREADY is sampled asserted. Note: EXCONCLOCK is a bit in the instruction. The loop counter is decremented by 2 every clock cycle if EXCONCLOCK=1, or if
  • Adaptec 1737100 | Programmer Manual - Page 59
    are available as outputs. The GFP is also capable of executing a write instruction, using the status data as the write data. The 32-bit status checked and is bad 14 FrameTypeNotSupported - If set, indicates frame type not supported. GFP is not able to calculate the checksum, or its not a TCP
  • Adaptec 1737100 | Programmer Manual - Page 60
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 5-1. Status/Control Register (Continued) Bit Description 16 StopTxDma - If set, indicates the transmit DMA engine must freeze its operation and wait for software intervention
  • Adaptec 1737100 | Programmer Manual - Page 61
    a block diagram of the Data Processing Unit. DataValid Frame Data Counter WR1 WR2 WR3 WR4 LC Frame Data Frame Processor Architecture Instruction Memory Data Data Instruction IP 8 Input Mux Mask Control 8 Input Mux Barrel Shifter Mask Control Input1 Input2 Simple ALU: Adder, Comparator Flag
  • Adaptec 1737100 | Programmer Manual - Page 62
    AIC-6915 Ethernet LAN Controller Programmer's Manual Instruction Formats Table 5-2 describes the Instruction Formats. Name Opcode 0 Opcode 1 Opcode 2 Opcode 3 Opcode 4 Opcode 5 Opcode 6 Opcode 7 Opcode 8 Opcode 9 Table 5-2. Instruction Formats Bit Number Description 3:0 Execute - Execute
  • Adaptec 1737100 | Programmer Manual - Page 63
    specified by GeneralReg2[7:0]. GFP implements two 16-bit internal registers, GeneralReg1 and GeneralReg2. It can access the registers by executing a 'Write' instruction to address x80 and x81. The first register stores the 2bit 'Type' assigned to each protocol, and the second stores the branch
  • Adaptec 1737100 | Programmer Manual - Page 64
    AIC-6915 Ethernet LAN Controller Programmer's Manual Name Opcode E Opcode F ExcOnClock ReqNextData LoadWR1 LoadWR2 LoadWR3 LoadWR4 LoadLC BarrelShifterCtrl MaskCtrl MaskSel MuxSelInput2 Table 5-2. Instruction Formats (Continued) Bit Number Description 3:0 Return - Return to main program. When
  • Adaptec 1737100 | Programmer Manual - Page 65
    Decrement1 (Input2 - Input1) '15'-'12' - Reserved [31:24] When the Opcode is a Branch to immediate command, then BranchAdd points to the next instruction memory location. If the command is Read/Write it indicates the target address. [47:32] General data 1 field. Data is also a control field for
  • Adaptec 1737100 | Programmer Manual - Page 66
  • Adaptec 1737100 | Programmer Manual - Page 67
    6 w w w w AIC-6915 Internal Registers Summary For the following registers, the 'Byte Address' indicates each registers location in memory space given as a byte offset address from the start of the memory space dedicated for internal registers - 0x50000h. PCI Configuration Header Registers Summary
  • Adaptec 1737100 | Programmer Manual - Page 68
    AIC-6915 Ethernet LAN Controller Programmer's Manual AIC-6915 Functional Registers Summary Mapped to address range 0x50040-0x500FF in memory space, address 0x40-0xFF in configuration space and address 0x40-0xFF in I/O
  • Adaptec 1737100 | Programmer Manual - Page 69
    AIC-6915 Internal Registers Summary Table 6-2. AIC-6915 Functional Registers Summary (Continued) Byte Offset (Hex) Register Name Comments 00B4 00B8 CompletionQueueHighAddr TxCompletionQueueCtrl Completion queue control and configuration registers 00BC RxCompletionQueue1Ctrl 00C0
  • Adaptec 1737100 | Programmer Manual - Page 70
    AIC-6915 Ethernet LAN Controller Programmer's Manual Additional PCI Registers Summary Mapped to address range 0x50FFF-0x50100 in Memory space. These registers can be accessed using memory or indirect I/O commands. Table 6-3. AIC-
  • Adaptec 1737100 | Programmer Manual - Page 71
    AIC-6915 Internal Registers Summary Table 6-4. AIC-6915 Additional Ethernet Registers Summary (Continued) Byte Offset (Hex) Register Name Comments 500C NonBkToBkIPG 5010 ColRetry 5014 MaxLength 5018 TxNibbleCnt 501C TxByteCnt 5020 ReTxCnt 5024 RandomNumGen 5028 MskRandomNum 502C-5033
  • Adaptec 1737100 | Programmer Manual - Page 72
  • Adaptec 1737100 | Programmer Manual - Page 73
    7 w w w w Register Descriptions Overview This section includes all the registers required for controlling, programming, and operating the AIC-6915. All registers throughout this section subscribe to the following format. 1248 Table 7-1. Shade Legends These bits or fields are under software
  • Adaptec 1737100 | Programmer Manual - Page 74
    AIC-6915 Ethernet LAN Controller Programmer's Manual AIC-6915 Address Space A device on a PCI bus can be header and AIC-6915 internal functional registers that are mostly accessed by the software driver during normal chip operation. 0x40000 0x4FFFF 64K Used for connecting an external device to
  • Adaptec 1737100 | Programmer Manual - Page 75
    PCI Address Map 0x7FFFF 64K Internal Registers Address Map 0xFFFF Reserved 0xE000 Ethernet FIFO Access 0xC000 Rx Frame Processor Instruction memory 0xA000 Memory and Indirect I/O access Reserved 0x60000 Internal registers (includes external PHY MII registers) (~16K words (~64KBytes)) 0x50000
  • Adaptec 1737100 | Programmer Manual - Page 76
    Ethernet LAN Controller Programmer's Manual Terminology Throughout this chapter, data values are defined as follows: s Byte = 8 bits s Halfword = 16 bits s Word = 32 bits s Doubleword = 64 bits AIC-6915 Internal Registers These registers are used by the software driver for configuration, control
  • Adaptec 1737100 | Programmer Manual - Page 77
    PCI Device Identifier registers contain product information for use by the HOST during system initialization and configuration. The two Device ID bytes contain an Adaptec product code. The default product code for the AIC-6915 is 6915h. This value can be changed to a value read from an external
  • Adaptec 1737100 | Programmer Manual - Page 78
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCI Command Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 04h - 05h Bit(s) rw 15:10 r 9 broadcast on the PCI bus. The AIC-6915 does not support special cycles as a target or master. MASTEREN: Master
  • Adaptec 1737100 | Programmer Manual - Page 79
    Register Descriptions Table 7-5. PCI Command Register (Continued) Bit(s) rw Reset Value Description/Function 0 r/w 0 ISPACEEN: I/O Space Enable. Setting this bit enables the AIC-6915 to respond to PCI I/O transactions. When ISPACEEN is inactive the AIC-6915 does not respond to I/O cycles.
  • Adaptec 1737100 | Programmer Manual - Page 80
    AIC-6915 Ethernet LAN Controller Programmer's Manual Bit(s) rw 11 r/w Table 7-6. PCI Status Register (Continued) Reset even when the transactions are not to the same agent. The AIC-6915 as a target supports Fast Back-To-Back transactions. TFBTBC is a read only bit. 0 Reserved: Always read
  • Adaptec 1737100 | Programmer Manual - Page 81
    Value Description/Function 7:0 r 00h PROGINFC[7:0]: The Program Interface register value identifies the specific register-level programming interface the agent supports. The PROGINFC for the first version of the AIC-6915 is identified as 00h. PCI Subclass Register Type: R Internal Registers
  • Adaptec 1737100 | Programmer Manual - Page 82
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCI Baseclass Register Type: R Internal Registers Subgroup: PCI CACHESIZE[7:0]: Cache Size [7:0] defines the cache line size (in 32bit words). Those word values supported are: 0, 4, 8, 16, 32 and 64. Any other value is treated as CACHESIZE
  • Adaptec 1737100 | Programmer Manual - Page 83
    bit address segment of the 64-bit address space. BASEADR0[18:4]: Indicates address space requirement, Always read as 0. Prefetchable: Always reads 0. Not supported. MemorySpaceAccessType[1:0]: Always read as 10. The AIC-6915 as a target may be located anywhere in a 64-bit address space. Memory Space
  • Adaptec 1737100 | Programmer Manual - Page 84
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCI HighBASEADR0 (Base Address 0) Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 14h - 17h Note: When an access is made to an address
  • Adaptec 1737100 | Programmer Manual - Page 85
    designed by another vendor and has another Vendors ID. The default value is the Adaptec Vendor ID number, 9004h. This value can be changed to a value read from an external ROM which may be used with a PCI device. The PCI supports an external ROM/EEPROM of 256-KBytes. When an access is made with
  • Adaptec 1737100 | Programmer Manual - Page 86
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-21. Expansion ROM Control Register Reset Bit(s) rw Value Description/Function 31:18 r/w 0 HOST can store information about the interrupt line connected to the device. The PCI bus supports four interrupt lines (INTA[D:A]). 7-14
  • Adaptec 1737100 | Programmer Manual - Page 87
    Register Descriptions PCI INTPINSEL (Interrupt Pin Select) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 3Dh Table 7-24. Interrupt Pin Select Register Reset Bit(s) rw Value Description/Function 7:0 r 1h INTPS[7:0]: The Interrupt Pin register specifies
  • Adaptec 1737100 | Programmer Manual - Page 88
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCI MAXLAT (Maximum Latency) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 3Fh Table 7-26. Maximum Latency Register Reset Bit(s) rw Value Description/
  • Adaptec 1737100 | Programmer Manual - Page 89
    : Setting this bit enables the device to assert a PCI interrupt (PCI_INTA_), else PCI interrupt is disabled. This bit must be set if the software driver wishes to receive any type of interrupts. 22:20 r/w 0 ExternalRegCsWidth: Indicates the width of the chip-select when an access to an external
  • Adaptec 1737100 | Programmer Manual - Page 90
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-27. PCIDeviceConfig Register (Continued) Reset Bit(s) rw Value in the FIFO. FIFOTHRESHOLD = 0 specifies a threshold of 256 bytes. The software driver should always use the default. 7 r/w 0 MemRdCmdEn: Controls when the PCI master
  • Adaptec 1737100 | Programmer Manual - Page 91
    master stops the transfer as soon as it detects/receives a data parity error. The PCIMstDmaEn, TxDmaEn and RxDmaEn bits are reset, and driver software intervention is required to resume operation. 5 r/w 0 AbortOnAddrParityErr: This bit controls the behavior of the PCI target state machine in
  • Adaptec 1737100 | Programmer Manual - Page 92
    AIC-6915 Ethernet LAN Controller Programmer's Manual BacControl Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 44h - 47h This register provides the software driver a way to configure and control BAC DMA operation. Table 7-28. BacControl Register Reset Bit
  • Adaptec 1737100 | Programmer Manual - Page 93
    Description/Function 31:24 r/w 23:16 r/w 15:0 r 0 PCIBusMaxLatency: Provides the peak PCI bus latency measured from the time the software driver reset the register. The latency is presented in PCICLKCYCLE*16 (480nSec) units. 0 PCIIntMaxLatency: Provides the peak PCI interrupt latency measured
  • Adaptec 1737100 | Programmer Manual - Page 94
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCIMonitor2 Register Type: R Internal Registers Subgroup: PCI device driver is able to use it. The AIC-6915 does not require special initialization. r 0 Auxiliary Power Source: This bit is only meaningful when PME_ is supported in D3
  • Adaptec 1737100 | Programmer Manual - Page 95
    Register Descriptions Table 7-31. Power Management Register (Continued) Reset Bit(s) rw Value Description/Function 18:16 r 1h PMVersion: This field indicates that there are 4 bytes of General Purpose Power Management registers implemented as described in revision 1.0 of the 'PCI Bus Power
  • Adaptec 1737100 | Programmer Manual - Page 96
    AIC-6915 Ethernet LAN Controller Programmer's Manual PME Event Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 58h- 5Bh Table 7-33. PME Event Register Reset Bit(s) rw Value Description/Function
  • Adaptec 1737100 | Programmer Manual - Page 97
    3 MAC address [7:0] --> MAC Addr Byte 2 MAC address [7:0] --> MAC Addr Byte 1 MAC address [7:0] --> MAC Addr Byte 0 (MSB) Minimum Grant [7:0] Maximum Latency [7:0] Reserved Adaptec Standard Format Checksum [7:0] Checksum [15:8] Value 04 90 15 69 00 02 04 90 08 = 62011/TX Rev. 0 09 = 62011/TX Rev
  • Adaptec 1737100 | Programmer Manual - Page 98
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCIComplianceTesting Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 64h - 67h This register is used for PCI compliance checker testing purposes only and
  • Adaptec 1737100 | Programmer Manual - Page 99
    is cleared the transmit module (data, buffer descriptors, completion descriptors) does not issue any DMA requests. The bit is cleared by the software driver, or when the PCI master encounters a PCI error which should disable the DMA operation. Note that only when the TXDMAEN bit is cleared can
  • Adaptec 1737100 | Programmer Manual - Page 100
    AIC-6915 Ethernet LAN Controller Programmer's Manual TimersControl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 74h - 77h Table 7-40. TimersControl Register Reset Bit(s) rw value Description/Function 31 r/w 0 EarlyRxQ1IntDelayDisable:
  • Adaptec 1737100 | Programmer Manual - Page 101
    its terminal count (0) the interrupts are enabled. '10' - Same as '01', except that new masking period starts automatically when the software driver clears both TXDONEINT and RXDONEINT. '11' - Same as '01', except that new masking period starts automatically when first asserting a new interrupt
  • Adaptec 1737100 | Programmer Manual - Page 102
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-40. TimersControl Register (Continued) Reset Bit(s) rw . If TimerClock period is 0.8 µs, then the range of CurrentTime is ~60 Min. The driver can load the register anytime in order to synchronize the current time of two adapter cards.
  • Adaptec 1737100 | Programmer Manual - Page 103
    GENERALTIMER count reached its terminal Count of zero. This bit is cleared on a read, or by writing a '1'. 0 SoftInt: This bit is set when the software driver writes a '1' to the Set Soft Interrupt bit in the GENERALCONTROL register. This bit is cleared by read, or by writing a '1'. 22 r/w 21
  • Adaptec 1737100 | Programmer Manual - Page 104
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-42. InterruptStatus Register (Continued) Reset 12 r/w 0 TxQueueDoneInt: Indicates that all frames scheduled for transmit by the software driver were fetched from host buffer and transferred into the internal FIFO. The AIC-6915 sets
  • Adaptec 1737100 | Programmer Manual - Page 105
    . 2 r/w 0 GfpRxInt: Indicates that the receive GFP has asserted the interrupt status bit. The GFP asserts the interrupt by executing a write instruction to address '0x0E'. 1 r/w 0 GfpTxInt: Indicates that the transmit GFP asserts the interrupt status bit. The GFP asserts the interrupt by
  • Adaptec 1737100 | Programmer Manual - Page 106
    AIC-6915 Ethernet LAN Controller Programmer's Manual ShadowInterruptStatus Register Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 84h - 87h This register is used for reading the Interrupt Status register in read-
  • Adaptec 1737100 | Programmer Manual - Page 107
    Register Descriptions InterruptEn Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 88h - 8Bh Specifies if the corresponding bit in INTERRUPTSTATUS register is enabled, causing an external PCI interrupt. The PCI interrupt bit must be enabled in the
  • Adaptec 1737100 | Programmer Manual - Page 108
    AIC-6915 Ethernet LAN Controller Programmer's Manual GPIO Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 8C - 8Fh The GPIO register provides for host software control of the GPIO[3:0] pins.
  • Adaptec 1737100 | Programmer Manual - Page 109
    : Always written as 0. 20:16 r/w 15:14 r 0 SkipLength: At the front of every frame/buffer transmit DMA descriptor there is a field reserved for software driver usage. The skip length field specifies that field size. The skip length is (SkipLength*8) bytes. If the field is 0, the skip length is
  • Adaptec 1737100 | Programmer Manual - Page 110
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-46. TxDescQueueCtrl Register (Continued) 128 byte '100' - 256 byte all other combinations are reserved. Note: When the software driver restricts the frame descriptor size, it must be aware that the maximum number of possible fragments
  • Adaptec 1737100 | Programmer Manual - Page 111
    :8]: When written with a nonzero value, this field indicates the starting address of the queue in host memory. It is written by the software driver during device initialization. The address must be aligned to a 256-byte boundary. The producer and consumer indices are pointing to a doubleword (8-byte
  • Adaptec 1737100 | Programmer Manual - Page 112
    AIC-6915 Ethernet LAN Controller Programmer's Manual TxDescQueueHighAddr Register Type: R/W Internal Registers Subgroup: as 0. 10:0 r/w 0 LoPrTxProducerIndex: Written by the software driver and read by the AIC-6915. When the software driver wants to transmit a frame, it adds the frame buffer
  • Adaptec 1737100 | Programmer Manual - Page 113
    in the low-priority DMA descriptor queue. The AIC-6915 increments HIPRTXCONSUMERINDEX after it completes the fetching of the descriptors from host memory. The software driver can write this field only if TXDMAEN is reset to '0'. In this case, the queue is disabled and the AIC-6915 cannot continue on
  • Adaptec 1737100 | Programmer Manual - Page 114
    AIC-6915 Ethernet LAN Controller Programmer's Manual TxDmaStatus2 Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: ACh- AFh Table 7-53. TxDmaStatus2 Register Reset Bit(s) rw Value Description/Function 31:29 r 0 FragmentCount:
  • Adaptec 1737100 | Programmer Manual - Page 115
    , the AIC-6915 PCI Master must use 64-bit addressing mode to access the queue. 6 r/w 0 TxCompletionProducerWe: When this bit is set, the software driver is able to write the transmit completion queue producer index. Otherwise, writes to the index are disabled. When the bit is cleared the queue
  • Adaptec 1737100 | Programmer Manual - Page 116
    AIC-6915 Ethernet LAN Controller Programmer's Manual Bit(s) 4 3:0 Table 7-56. TxCompletionQueueCtrl Register (Continued) Reset rw starting address of the queue in host memory. It is written by the host driver during initialization and read by the AIC-6915. The amount of host memory allocated for
  • Adaptec 1737100 | Programmer Manual - Page 117
    /Function 31:8 r/w x RxCompletionQ2BaseAddress[31:8]: This field contains the starting address of the queue in host memory. It is written by the host driver during initialization and read by the AIC-6915. The amount of host memory allocated for the completion queue is either 4-KBytes or 8-KBytes
  • Adaptec 1737100 | Programmer Manual - Page 118
    AIC-6915 Ethernet LAN Controller Programmer's Manual CompletionQueueConsumerIndex Type: R/W Internal Registers Subgroup: Ethernet 25:16 r/w 0 TxCompletionConsumerIndex: Written by the software driver and read by the AIC-6915. The software driver increments or writes a new index to free space in
  • Adaptec 1737100 | Programmer Manual - Page 119
    31:26 r 0 Reserved: Always read and written as zero. 25:16 r/w 0 TxCompletionProducerIndex: Written by the AIC-6915 and read by the host driver. The AIC-6915 increments the index by 1 whenever a completion descriptor is successfully DMA-transferred to the transmit (or shared) completion list in
  • Adaptec 1737100 | Programmer Manual - Page 120
    6915 Ethernet LAN Controller Programmer's Manual Bit(s) 9:0 Table 7-61. RxHiPrCompletionPtrs Register (Continued) Reset rw Value Description/Function r/w 0 RxCompletionQ2ConsumerIndex: Written by software driver and read by the AIC-6915. The software driver increments or writes a new index
  • Adaptec 1737100 | Programmer Manual - Page 121
    must first disable RXDMA (by writing to the GENERALCTRL register), then wait until it reads a 1 from NOBURSTSTATE. The driver can then write RXDMACRC and reenable RXDMA. 17 r 0 Reserved: Always written as zero. 16:12 r/w 0 RxEarlyIntThreshold[4:0]: This field specifies the number of bytes
  • Adaptec 1737100 | Programmer Manual - Page 122
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-62. RxDmaCtrl Register (Continued) Reset Bit(s) by the internal arbiter (BAC) to determine which module (transmit or receive) to service next. The programmable threshold in bytes is 16 * RXHIGHPRIORITYFIFOTHRESHOLD. 7 r 0 RxFpTestMode
  • Adaptec 1737100 | Programmer Manual - Page 123
    All other combinations are reserved. These control bits are used for both descriptor queues. 7 r/w 0 RxQ1ConsumerWe: When this bit is set, the software driver is able to write and update the buffer descriptor queue 1 consumer index. When the bit is cleared, the Consumer Index is write-protected
  • Adaptec 1737100 | Programmer Manual - Page 124
    AIC-6915 Ethernet LAN Controller Programmer's Manual RxDescQueue2Ctrl Type: R/W Internal Registers Subgroup: Ethernet Functional The lower 8 bits of address must be 0. This register is written by host driver during initialization and read by the AIC-6915 during a receive DMA operation. Note: The address
  • Adaptec 1737100 | Programmer Manual - Page 125
    8 bits of the address must be 0. This field is written by host driver during initialization and read by the AIC-6915 during a receive DMA operation. Note of the last descriptor read by the AIC-6915. The software driver should use the ENDINDEX value in the receive completion descriptor rather that
  • Adaptec 1737100 | Programmer Manual - Page 126
    AIC-6915 Ethernet LAN Controller Programmer's Manual RxDescQueue2Ptrs Type: R/W Internal Registers Subgroup: Ethernet new receive data burst until RXDMA is enabled. This bit should be read if the driver wishes to write to RXDMACRC without resetting the AIC-6915. 15:0 r/w 0 RxFramesLostCount:
  • Adaptec 1737100 | Programmer Manual - Page 127
    by the RXADDRESSFILTERINGCTRL register and various address filtering memories, determines which frames are accepted by the AIC-6915 and passed to the driver. The frame's destination address is compared against the following three criteria. If the address matches any of these criteria, the frame is
  • Adaptec 1737100 | Programmer Manual - Page 128
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-71. RxAddressFilteringCtrl Register Reset Bit(s) rw Value Description/Function 31:16 Reserved Note: The VLAN tag can be provided to the driver in the completion descriptor if the appropriate RXCOMPLETIONQUEUE2TYPE is selected. 7-56
  • Adaptec 1737100 | Programmer Manual - Page 129
    Register Descriptions Bit(s) 7:6 5:4 3 2 1 0 Table 7-71. RxAddressFilteringCtrl Register (Continued) Reset rw Value Description/Function r/w 0 PerfectFilteringMode[1:0] '00' - Perfect filtering disabled. '01' - 16 perfect addresses filtering. The AIC-6915 compares the incoming frame
  • Adaptec 1737100 | Programmer Manual - Page 130
    AIC-6915 Ethernet LAN Controller Programmer's Manual RxFrameTestOut Register Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: F8h- FBh Table 7-72. RxFrameTestOut Register Reset Bit(s) rw Value Description/Function 31:24 r 0
  • Adaptec 1737100 | Programmer Manual - Page 131
    Byte Address: 0100h - 0103h This register is for diagnostic purposes only. When the AIC-6915 responds with a target abort, the software driver can determine the reason by reading this register. Table 7-73. PCITargetStatus Register Reset Bit(s) rw value Description/Function 31 r 0 Reserved
  • Adaptec 1737100 | Programmer Manual - Page 132
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCIMasterStatus1 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0104h - 0107h This register is used for diagnostic purposes to read the internal status
  • Adaptec 1737100 | Programmer Manual - Page 133
    Register Descriptions PCIMasterStatus2 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0108h-010Bh Table 7-75. PCIMasterStatus2 Register Reset Bit(s) rw Value Description/Function 31:26 r 0 Reserved: Always read as 0. 25 r x System64: Provides the
  • Adaptec 1737100 | Programmer Manual - Page 134
    AIC-6915 Ethernet LAN Controller Programmer's Manual BacDmaDiagnostic0 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0110h - 0113h Table 7-77. BACDMADiagnostic0 Register Reset Bit(s) rw Value Description/Function 31:29 r 0
  • Adaptec 1737100 | Programmer Manual - Page 135
    Register Descriptions BacDmaDiagnostic2 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0118h - 011Bh This register provides information about the current DMA transfer and is used for diagnostic purposes only. All values in the register are synchronized to the
  • Adaptec 1737100 | Programmer Manual - Page 136
    AIC-6915 Ethernet LAN Controller Programmer's Manual BacDmaDiagnostic3 Register Type: R Internal Registers Subgroup: PCI Functional Registers Byte Address: 011Ch - 011Fh Table 7-80. BACDMADiagnostic3 Register Reset Bit(s) rw Value Description/Function 31:25 r 0
  • Adaptec 1737100 | Programmer Manual - Page 137
    r/w 0 MacAddr[47:32]: The MAC address of the AIC-6915 is read from the external serial EPROM and loaded to the MACADDR register. The software driver can overwrite the value by writing to this register. The transmit engine uses the address to create the media header when selecting an ECB descriptor
  • Adaptec 1737100 | Programmer Manual - Page 138
    AIC-6915 Ethernet LAN Controller Programmer's Manual PCI CardBus Registers The following registers are defined in the CardBus PC Card Electrical Specification. Their implementation in the AIC-6915 is described here. For
  • Adaptec 1737100 | Programmer Manual - Page 139
    from somewhere in the chip other than the FORCEFUNCTION register. 14:5 r 4 r 0 Reserved: Always reads 0. 0 GWake: Always 0. The AIC-6915 does not support wakeup on CardBus as it requires an external power source. 2:3 r 1 r 3 BVD[2:1]: Always 0 x 3 (11b). The card containing the AIC-6915 is
  • Adaptec 1737100 | Programmer Manual - Page 140
    6915 Ethernet LAN Controller Programmer's Manual ForceFunction Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 013Ch - 013Fh Setting a bit here also sets a bit in the FunctionPresentState register. Since only the interrupt function is supported, only bit 15 is
  • Adaptec 1737100 | Programmer Manual - Page 141
    reads any address within the range, the reserved bits are all '0' except bit '31' which provides the 'MiiBusy' status. When the software driver accesses the port and the Serial MII Management port is idle, the AIC-6915 sets the MiiBusy bit and starts an access to the appropriate
  • Adaptec 1737100 | Programmer Manual - Page 142
    AIC-6915 Ethernet LAN Controller Programmer's Manual TestMode Register (TBD) Type: R/W Internal Registers Subgroup: Ethernet Extra Registers Byte Address: 4000h - 4003h This register controls test mode of the chip. Table 7-88. TestMode
  • Adaptec 1737100 | Programmer Manual - Page 143
    Register Descriptions MAC Control Registers MacConfig1 Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5000h - 5003h Table 7-91. MacConfig1 Register Reset Bit(s) rw Value Description/Function 31:16 r/w 0 Reserved: Always read as 0. 15 r/w 0 SoftRst: Software
  • Adaptec 1737100 | Programmer Manual - Page 144
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-91. MacConfig1 Register (Continued) Reset Bit(s) rw Value inserted in order to pad the packet to 60 bytes. For each packet the software driver may request the AIC-6915 to calculate and add the 4-bytes CRC to the Ethernet
  • Adaptec 1737100 | Programmer Manual - Page 145
    Register Descriptions MacConfig2 Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5004h- 5007h Table 7-92. MacConfig2 Register Reset Bit(s) rw Value Description/Function 31:16 r/w 0 Reserved: Always read as 0. 15 r 0 TxCRCerr: Transmit Ethernet CRC error status
  • Adaptec 1737100 | Programmer Manual - Page 146
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-92. MacConfig2 Register (Continued) Reset Bit(s) rw Value Description/Function 2 r/w 0 TxISLEn: Enables ISL function. When this bit is cleared, regular Ethernet frames are transmitted
  • Adaptec 1737100 | Programmer Manual - Page 147
    Register Descriptions NonBkToBkIPG Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 500Ch- 500Fh Table 7-94. NonBkToBkIPG Register Reset Bit(s) rw Value Description/Function 31:15 r/w 0 Reserved: Always reads 0. 14:8 r/w 0Ch IPGR1: For a non back-to-back
  • Adaptec 1737100 | Programmer Manual - Page 148
    AIC-6915 Ethernet LAN Controller Programmer's Manual MaxLength Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5014h - 5017h Bit(s) 31:16 15:0 Table 7-96. MaxLength Register Reset rw Value Description/Function r/w 0
  • Adaptec 1737100 | Programmer Manual - Page 149
    Register Descriptions ReTxCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5020h- 5023h Table 7-99. ReTxCnt Register Reset Bit(s) rw Value Description/Function 31:4 r/w 0 Reserved: Always read as 0. 3:0 r/w 0 ReTxCnt: This counter keeps track of the number
  • Adaptec 1737100 | Programmer Manual - Page 150
    AIC-6915 Ethernet LAN Controller Programmer's Manual MskRandomNum Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5028h - 502Bh Table 7-101. MskRandomNum Register Reset Bit(s) rw Value Description/Function 31:10 r/w 0 Reserved:
  • Adaptec 1737100 | Programmer Manual - Page 151
    Register Descriptions RxByteCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5040h- 5043h Table 7-103. RxByteCnt Register Reset Bit(s) rw Value Description/Function 31:16 r/w 0 Reserved: Always reads 0. 15:0 r/w 0 RxByteCnt: This is a multipurpose counter
  • Adaptec 1737100 | Programmer Manual - Page 152
    AIC-6915 Ethernet LAN Controller Programmer's Manual MIIStatus Register Type: R/W Internal Registers Subgroup: MAC AIC-6915) are latched, and the MIIDATAVALID bit is set, indicating to the software driver that valid data is ready. Any read or write to the MIIREGISTERSACCESSPORT resets the bit,
  • Adaptec 1737100 | Programmer Manual - Page 153
    Register Descriptions Since each external PHY takes up 128 bytes (32 x 32 bits), the actual address offset to access each of them through the AIC-6915 is: Table 7-107. External PHY Address Examples External PHY Byte Address PHY # 0 2000h PHY # 1 2080h PHY # 2 2100h PHY # 3 2180h PHY # 4
  • Adaptec 1737100 | Programmer Manual - Page 154
    AIC-6915 Ethernet LAN Controller Programmer's Manual Address Filtering Registers Perfect Address Memory Register Type: R/W Internal Registers Subgroup: Address Filtering Memory Access Byte Address: 6000h - 6FFFh Table 7-108 starts at byte address
  • Adaptec 1737100 | Programmer Manual - Page 155
    Register Descriptions byte (h) word (h) 2C0 B0 2D0 B4 2E0 B8 2F0 BC Table 7-108. Address Filtering Memory (Continued) word -> 3 2 1 Internal 463-448 Internal 479-464 Internal 495-480 Internal 511-496 0 463-448 479-464 495-480 511-496 Perfect Addresses The AIC-6915 compares
  • Adaptec 1737100 | Programmer Manual - Page 156
    AIC-6915 Ethernet LAN Controller Programmer's Manual MAC Statistic Registers Type: R/W Internal Registers Subgroup: MAC optional. All the "M" and "R" fields are supported. All the "O" fields are listed in descending priority order of support. Table 7-109. MAC Statistic Register Byte Addr
  • Adaptec 1737100 | Programmer Manual - Page 157
    Register Descriptions Table 7-109. MAC Statistic Register (Continued) Byte Addr Statistics Source Priority Bits Descriptions 34h Frames Lost due to TX Internal Transmit Errors. (Cannot recover from FIFO underrun) R 32 Count the number of frames which are lost in transmit engine
  • Adaptec 1737100 | Programmer Manual - Page 158
    AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-109. MAC Statistic Register (Continued) Byte Addr Statistics Source Priority Bits Descriptions 6Ch Receive Packets 128 to 255 Bytes MAC (RX) RMON 32 Count
  • Adaptec 1737100 | Programmer Manual - Page 159
    Processor Register Reset Bit(s) rw Value Description/Function 31:0 r/w x RxGfpMem: This field defines a 256-byte address space that the software driver can use to access the receive GFP program memory. Ethernet FIFO Type: R/W Internal Registers Subgroup: Ethernet FIFO Byte Address: C000h
  • Adaptec 1737100 | Programmer Manual - Page 160
  • Adaptec 1737100 | Programmer Manual - Page 161
    documentation is intended as a guide for the software developer writing a device driver for the Adaptec AIC-6915 Ethernet Network Controller. It is designed to complement the driver source code in the DDK and to serve as a basic checklist for driver development. Initialization of the controller
  • Adaptec 1737100 | Programmer Manual - Page 162
    AIC-6915 Ethernet LAN Controller Programmer's Manual Producer-Consumer Model for the AIC-6915 The AIC-6915 uses the Producer-Consumer model for its operation and interaction with the driver. One of the entities (AIC-6915 or the driver) "Produces" work items by placing them in a shared queue, the
  • Adaptec 1737100 | Programmer Manual - Page 163
    -6915 Device ID (6915) and Vendor ID (9004). Example: // Windows NT driver example // Find the AIC-6915 card in PCI space // This assumes that the be accessed through PCI configuration cycles. All other register access in the driver contained in the DDK is memory-mapped. The AIC-6915 does offer
  • Adaptec 1737100 | Programmer Manual - Page 164
    AIC-6915 Ethernet LAN Controller Programmer's Manual 1 PCI COMMAND Register (offset 04h): The PCI to be repeated for a reset operation. 3 PHY Reset: PHY initialization in the sample driver is based on the Seeq Technology Incorporated 80220/80221 100BASE-TX/10BASE-T Ethernet Media Interface Adapter
  • Adaptec 1737100 | Programmer Manual - Page 165
    . Either this interrupt or TxFrameCompleteInt or TxQueueDoneInt must be set to generate transmit interrupts. Example: // Windows NT driver example of driver reset. // The board has already been discovered. // Reset the PHY InitAutonegotiate(); // Initialize GeneralEthernetCtrl register to stop any
  • Adaptec 1737100 | Programmer Manual - Page 166
    AIC-6915 Ethernet LAN Controller Programmer's Manual // Other fields in MacConfig1 may remain at the default value AIC6915_WRITE_REG(Adapter->RegisterBaseVa->MacConfig1, MacConfig1Value); // Read MacConfig1 again AIC6915_READ_REG(MacConfig1, MacConfig1Value); // Now do a soft reset
  • Adaptec 1737100 | Programmer Manual - Page 167
    -transferred to host memory, the AIC-6915 adds a new entry to the Receive Completion Descriptor Queue. The memory for this queue is allocated by the driver and is passed to AIC-6915 via the RXCOMPLETIONQUEUE1CTRL register (offset BCh). The size of this queue is fixed at 1024 entries. There are four
  • Adaptec 1737100 | Programmer Manual - Page 168
    LAN Controller Programmer's Manual Type 2 Completion It also contains an END bit, which is used by the driver to indicate the end of the buffer queue when the receive polling This buffer descriptor is useful when the operating system supports 64-bit addressing. The 64-bit Receive Buffer Descriptor
  • Adaptec 1737100 | Programmer Manual - Page 169
    which must be defined before the AIC-6915 can begin to receive packets. These registers and the fields which must be initialized in the driver are summarized below for the case of 32-bit addressing. Control bit fields which require initialization are described. Register bits which are not explicitly
  • Adaptec 1737100 | Programmer Manual - Page 170
    AIC-6915 Ethernet LAN Controller Programmer's Manual 1 RXCOMPLETIONQUEUE1CTRL (offset BCh): This register is used to define the location and type of the first Receive Completion Descriptor Queue. Required Fields: - RxCompletionQ1BaseAddress: Assign the
  • Adaptec 1737100 | Programmer Manual - Page 171
    Sample Driver 6 RXDMACTRL (offset D0h): This register controls receive DMA operation and frame acceptance criteria. Required Fields: - RxCompletionQ2Enable: Enable the second Receive Completion Descriptor Queue if needed. -
  • Adaptec 1737100 | Programmer Manual - Page 172
    AIC-6915 Ethernet LAN Controller Programmer's Manual 11 RXDESCQUEUE1PTRS (offset E8h): This register contains the criteria. The exact settings depend on the address filtering appropriate for the driver environment. Example: // Receive initialization example // 4 byte Receive Completion Descriptors
  • Adaptec 1737100 | Programmer Manual - Page 173
    Sample Driver // assign the base address of the completion queue (high 24 bits) RxCompletionQueue1CtrlValue.RxCompletionQ1BaseAddress = NdisGetPhysicalAddressLow(RxCompletionQ) >> 8; // Write the value to the AIC-6915 AIC6915_WRITE_REG(Adapter->RegisterBaseVa->
  • Adaptec 1737100 | Programmer Manual - Page 174
    AIC-6915 Ethernet LAN Controller Programmer's Manual 8-14 // If single queue, use the first queue only // Initialize RxDescQueue1LowAddress // Allocate memory for RxDescQueue1 AIC6915_ALLOC_MEMORY(&Status, &RxDescQ, 4 * 2048); // 4 byte descriptor, //2K fixed size queue
  • Adaptec 1737100 | Programmer Manual - Page 175
    . In this Receive Completion Descriptor, the ENDINDEX field is an index to the Receive Buffer Descriptor which contains the packet just received. The driver uses this index to extract the Receive Buffer containing the packet just received. The packet length and receive status are also contained in
  • Adaptec 1737100 | Programmer Manual - Page 176
    AIC-6915 Ethernet LAN Controller Programmer's Manual // RxBufferRing structure contains pointers to physical and virtual // or a TXQUEUEDONE interrupt, depending on which interrupt has been enabled in the driver. If dual transmit queues are implemented, a single Transmit Completion Descriptor Queue
  • Adaptec 1737100 | Programmer Manual - Page 177
    segment below, and the Receive Architecture section of this manual. Transmit Buffer Descriptor Queue Four different Transmit Buffer Descriptor that the operating system passes a packet containing 3 buffers to the driver. If the driver has determined that this packet will not completely fit into the
  • Adaptec 1737100 | Programmer Manual - Page 178
    AIC-6915 Ethernet LAN Controller Programmer's Manual of descriptor. These descriptors are outlined below. For type is a frame descriptor, it can contain all of the buffers in a given packet. The driver must determine the size of each descriptor to convert the Transmit Producer or Consumer index to a
  • Adaptec 1737100 | Programmer Manual - Page 179
    size must be a multiple of 8 bytes. Since this descriptor type is a frame descriptor, it can contain all of the buffers in a given packet. The driver must determine the size of each descriptor to convert the Transmit Producer or Consumer index to a software array index. When calculating the size of
  • Adaptec 1737100 | Programmer Manual - Page 180
    AIC-6915 Ethernet LAN Controller Programmer's Manual To convert the hardware Transmit Producer or Consumer Since the software is the producer of Transmit Buffer Descriptors, it is the responsibility of the driver to determine the priority of a given Transmit Buffer and to place it in the appropriate
  • Adaptec 1737100 | Programmer Manual - Page 181
    set of registers which must be initialized in preparation for transmitting packets. These registers and the fields which must be initialized in the driver are summarized below. Register bits which are not explicitly described here may be left at the default reset value. The developer must determine
  • Adaptec 1737100 | Programmer Manual - Page 182
    Manual 5 TXDESCQUEUEPRODUCERINDEX (offset A0h): This register contains the producer index for both the high and low priority Transmit Buffer Descriptor Queues. These fields are incremented in software whenever the driver is normally not changed by the driver. Required Fields: - TransmitThreshold: If
  • Adaptec 1737100 | Programmer Manual - Page 183
    used only if two receive completion queues are implemented. In this case, RxCompletionQ2ConsumerIndex should be initialized to zero. Example: // Windows NT driver example // Single Transmit Completion and Buffer Descriptor Queues // Type 1 32 bit buffer descriptors with an 8-byte skip field // First
  • Adaptec 1737100 | Programmer Manual - Page 184
    AIC-6915 Ethernet LAN Controller Programmer's Manual // Set up the low 32 bits of the low priority transmit descriptor queue // base address LoPrTxDescQBaseAddrValue = NdisGetPhysicalAddressLow(Adapter->TxDescRing.AlignedPa); AIC6915_WRITE_REG(LoPrTxDescQBaseAddr, LoPrTxDescQBaseAddrValue); // Set
  • Adaptec 1737100 | Programmer Manual - Page 185
    must set up the Transmit Buffer Descriptor(s) for all buffers in this packet, and then instruct the AIC-6915 controller to transmit the packet. Example: // Windows NT driver example // Type 1 Transmit Buffer Descriptor // Single Transmit Buffer Descriptor Queue (low priority) // 8 byte skip field
  • Adaptec 1737100 | Programmer Manual - Page 186
    AIC-6915 Ethernet LAN Controller Programmer's Manual 8-26 Adapter->MapRegisterIndex, TRUE, PhysicalSegmentArray, &BufferPhysicalSegments); // Put each physical segment for this buffer into a Transmit Buffer // Descriptor for (ii = 0 ; ii < BufferPhysicalSegments; ii++) { PhysicalAddressUnit =
  • Adaptec 1737100 | Programmer Manual - Page 187
    transmitted a packet, it places that packet in the Transmit Completion Descriptor Queue and initiates a TXFRAMECOMPLETE interrupt or a TXDMADONE interrupt. The driver must process this interrupt and return the transmitted packet resource to the operating system. In the code fragment below, we have
  • Adaptec 1737100 | Programmer Manual - Page 188
    AIC-6915 Ethernet LAN Controller Programmer's Manual // The index is a multiple of the size of the Transmit Buffer Descriptor. IndexToDescriptor = TxCompletionDesc->ConsumerIndex/ sizeof(AIC6915_TX_DESC); TxDesc = Adapter->TxDesc[IndexToDescriptor]; // Return the packet to
  • Adaptec 1737100 | Programmer Manual - Page 189
    Filtering Implemented In NDIS 5.0 driver TCP Checksum For Transmitted Packets Implemented In NDIS 5.0 driver Transmit Buffer Descriptor Type Type Not implemented *Additional interrupts not enabled in DDK driver: GpioInt, StatisticWrapInt, PhyInt, AbNormalInterrupt, GeneralTimerInt, SoftInt
  • Adaptec 1737100 | Programmer Manual - Page 190
    AIC-6915 Ethernet LAN Controller Programmer's Manual DDK Development Environment The drivers contained in the DDK were written for the Windows NT environment. There is an NDIS 3.0/4.0 driver and an NDIS 5.0 driver in the DDK. They were developed using Version 5.0 of the Microsoft Visual C++ compiler
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Document Title: ABA-1030 DVB Satellite Receiver
Stock Number: 512130-00, Rev. A
Cover-1
Print Spec Number: 497767-00, Rev. AA
Current Date: 10/10/98
Programmer’s Manual
AIC-6915
Ethernet LAN Controller
R